Chang-Hyun Kim
This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.
Bibliography
2024
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference.
ACM Trans. Design Autom. Electr. Syst., March, 2024
Comparative Analysis of Integrated Filtering Methods Using UWB Localization in Indoor Environment.
Sensors, February, 2024
Optimal Control for a Superconducting Hybrid MagLev Transport System with Multirate Multisensors in a Smart Factory.
Sensors, January, 2024
Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning.
IEEE Access, 2024
2023
Trampoline Stiffness Estimation by Using Robotic System for Quantitative Evaluation of Jumping Exercises.
Sensors, December, 2023
Fault Diagnosis Method for Human Coexistence Robots Based on Convolutional Neural Networks Using Time-Series Data Generation and Image Encoding.
Sensors, December, 2023
IEEE Robotics Autom. Lett., 2023
TORCWA: GPU-accelerated Fourier modal method and gradient-based optimization for metasurface design.
Comput. Phys. Commun., 2023
Towards long-tailed, multi-label disease classification from chest X-ray: Overview of the CXR-LT challenge.
CoRR, 2023
IEEE Access, 2023
BL-PIM: Varying the Burst Length to Realize the All-Bank Performance and Minimize the Multi-Workload Interference for in-DRAM PIM.
IEEE Access, 2023
DESEM: Depthwise Separable Convolution-Based Multimodal Deep Learning for In-Game Action Anticipation.
IEEE Access, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
Proceedings of the 35th IEEE Hot Chips Symposium, 2023
A Comparative Study on the Failure Detection Methods Using Time-Series Data Image Generation and CNN for Driving Module of Cobots.
Proceedings of the 9th International Conference on Control, 2023
2022
Low-overhead inverted LUT design for bounded DNN activation functions on floating-point vector ALUs.
Microprocess. Microsystems, September, 2022
Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests.
IEEE Trans. Parallel Distributed Syst., 2022
A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Three-Dimensional Foot Position Estimation Based on Footprint Shadow Image Processing and Deep Learning for Smart Trampoline Fitness System.
Sensors, 2022
UVtac: Switchable UV Marker-Based Tactile Sensing Finger for Effective Force Estimation and Object Localization.
IEEE Robotics Autom. Lett., 2022
Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling.
IEEE Access, 2022
Encoded Image-Based Time Series Classification for Improving Colorimetric Detection of Hydrogen Sulfide (H2S).
Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022
Tremor Feature Extraction for Enhanced Interpretability of Vocal Disease Classification.
Proceedings of the Pattern Recognition, Computer Vision, and Image Processing. ICPR 2022 International Workshops and Challenges, 2022
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
2021
Sensors, 2021
Applying Piecewise Linear Approximation for DNN Non-Linear Activation Functions to Bfloat16 MACs.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
2020
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.
IEEE J. Solid State Circuits, 2020
x64Unpack: Hybrid Emulation Unpacker for 64-bit Windows Environments and Detailed Analysis Results on VMProtect 3.4.
IEEE Access, 2020
2019
Fundamental Experiment on Relationship Between External Force and Light Intensity in Soft Tactile Sensor Using Sponge.
Proceedings of the International Conference on Systems, Signals and Image Processing, 2019
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Sensor Offset Compensation for Improved Levitation Performance of Passive Maglev Transport System.
Proceedings of the IECON 2019, 2019
A Fundamental Experiment on Contact Position Estimation on Vision based Dome-type Soft Tactile Sensor using Ready-made Medium.
Proceedings of the 13th International Conference on Sensing Technology, 2019
DeepHiR: improving high-radix router throughput with deep hybrid memory buffer microarchitecture.
Proceedings of the ACM International Conference on Supercomputing, 2019
2018
Wirel. Pers. Commun., 2018
Wirel. Pers. Commun., 2018
Experimental Verification of a Magnetic Levitation Transport System for the OLED Display Evaporation Process Under Vacuum.
IEEE Robotics Autom. Lett., 2018
Computational prediction of the effects of the intra-aortic balloon pump on heart failure with valvular regurgitation using a 3D cardiac electromechanical model.
Medical Biol. Eng. Comput., 2018
Analysis of Load Unbalance According to Topology of Bipolar Low Voltage DC Distribution System.
Proceedings of the TENCON 2018, 2018
2017
Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017
Proceedings of the 11th Asian Control Conference, 2017
Development of high accuracy of magnetic levitation transport system for OLED evaporation process.
Proceedings of the IEEE International Conference on Advanced Intelligent Mechatronics, 2017
2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
2015
Proceedings of the 7th International Conference on Cybernetics and Intelligent Systems, 2015
16.6 Double-side CMOS-CNT biosensor array with padless structure for simple bare-die measurements in a medical environment.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Joint Estimation of Multiple Notes and Inharmonicity Coefficient Based on ${f_0}$-Triplet for Automatic Piano Transcription.
IEEE Signal Process. Lett., 2014
KSII Trans. Internet Inf. Syst., 2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
2013
IEEE Signal Process. Lett., 2013
Proceedings of the 44th Internationel Symposium on Robotics, 2013
2012
A novel elliptical curve ID cryptography protocol for multi-hop ZigBee sensor networks.
Wirel. Commun. Mob. Comput., 2012
Implement Real-Time Polyphonic Pitch Detection and Feedback System for the Melodic Instrument Player.
Proceedings of the Neural Information Processing - 19th International Conference, 2012
2011
IEEE Signal Process. Lett., 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
A 31 ns Random Cycle VCAT-Based 4F <sup>2</sup> DRAM With Manufacturability and Enhanced Cell Efficiency.
IEEE J. Solid State Circuits, 2010
IEEE J. Solid State Circuits, 2010
A comparison of the Newton-Krylov method with high order Newton-like methods to solve nonlinear systems.
Appl. Math. Comput., 2010
Proceedings of the International Conference on Information and Communication Technology Convergence, 2010
Proceedings of the International Conference on Image Processing, 2010
Proceedings of the International Conference on Image Processing, 2010
2009
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure.
IEEE J. Solid State Circuits, 2009
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.
IEEE J. Solid State Circuits, 2009
Comput. Commun., 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the 2009 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2009
Improvement on learning-based super-resolution by adopting residual information and patch reliability.
Proceedings of the International Conference on Image Processing, 2009
2008
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
Proceedings of the 22nd Pacific Asia Conference on Language, Information and Computation, 2008
Proceedings of the 22nd Pacific Asia Conference on Language, Information and Computation, 2008
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits, 2007
Worker Safety Management System over Wireless Sensor Network.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007
Proceedings of the 21st Pacific Asia Conference on Language, Information and Computation, 2007
Proceedings of Machine Translation Summit XI: Papers, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Evolving Compact and Interpretable Takagi-Sugeno Fuzzy Models With a New Encoding Scheme.
IEEE Trans. Syst. Man Cybern. Part B, 2006
A 512-mb DDR3 SDRAM prototype with C<sub>IO</sub> minimization and self-calibration techniques.
IEEE J. Solid State Circuits, 2006
A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter.
IEEE J. Solid State Circuits, 2006
Proceedings of the 32nd International Conference on Very Large Data Bases, 2006
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the Advances in Natural Language Processing, 2006
Proceedings of the Advances in Natural Language Processing, 2006
2005
A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling.
IEEE J. Solid State Circuits, 2005
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems.
IEEE J. Solid State Circuits, 2005
Evolving structure and parameters of fuzzy models with interpretable membership functions.
J. Intell. Fuzzy Syst., 2005
IEICE Trans. Electron., 2005
Proceedings of Machine Translation Summit X: Papers, 2005
2004
A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration.
IEEE J. Solid State Circuits, 2004
Evolutionary optimization of fuzzy systems for water level control in the steam generator of nuclear power plant.
Proceedings of the IEEE International Conference on Systems, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
Artif. Life Robotics, 2003
Evolutionary Optimization of Fuzzy Models with Asymmetric RBF Membership Functions Using Simplified Fitness Farrugia.
Proceedings of the Fuzzy Sets and Systems - IFSA 2003, 10th International Fuzzy Systems Association World Congress, Istanbul, Turkey, June 30, 2003
Proceedings of the Information Networking, 2003
A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
IEEE J. Solid State Circuits, 2002
Proceedings of the 16th Pacific Asia Conference on Language, Information and Computation, 2002
Proceedings of the 2002 IEEE International Conference on Robotics and Automation, 2002
Proceedings of the Machine Translation: From Research to Real Users, 2002
2001
A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity.
IEEE J. Solid State Circuits, 2001
IEEE J. Solid State Circuits, 2001
2000
IEEE J. Solid State Circuits, 2000
1999
IEEE J. Solid State Circuits, 1999
IEEE J. Solid State Circuits, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme.
IEEE J. Solid State Circuits, 1998
A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system.
IEEE J. Solid State Circuits, 1998
1997
IEEE J. Solid State Circuits, 1997
Low-voltage electronics for the stimulation of biological neural networks using fully complementary BiCMOS circuits.
IEEE J. Solid State Circuits, 1997
1996
IEEE J. Solid State Circuits, 1996
IEEE J. Solid State Circuits, 1996
1991
Proceedings of the First Great Lakes Symposium on VLSI, 1991