Soo-In Cho

Affiliations:

Samsung Electronics Company Ltd., Hwasung, South Korea

According to our database¹, Soo-In Cho authored at least 21 papers between 1994 and 2009.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2009

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

2008

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

2007

A DLL with Jitter-Reduction Techniques for DRAM Interfaces.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 512-mb DDR3 SDRAM prototype with C<sub>IO</sub> minimization and self-calibration techniques.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

2005

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

2003

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2002

2001

A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2001

A dual-loop delay-locked loop using multiple voltage-controlled delay lines.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2001

2000

A low-jitter mixed-mode DLL for high-speed DRAM applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

1999

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1999

A 1-Gb/s bidirectional I/O buffer using the current-mode scheme.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1999

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1999

1998

A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1998

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1998

1997

Low-voltage, high-speed circuit designs for gigabit DRAMs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1997

1996

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1996

1994

16-Mb synchronous DRAM with 125-Mbyte/s data rate.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, April, 1994

Soo-In Cho

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