Yoji Bando

According to our database1, Yoji Bando authored at least 9 papers between 2009 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2015
A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.
IEEE J. Solid State Circuits, 2015

2013
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation.
IEICE Trans. Electron., 2013

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
On-Chip In-Place Measurements of V<sub>th</sub> and Signal/Substrate Response of Differential Pair Transistors.
IEICE Trans. Electron., 2012

2011
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement.
IEICE Trans. Electron., 2011

A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits.
IEICE Trans. Electron., 2011

Microprocessor power noise measurements with different levels of resource occupancy.
IEICE Electron. Express, 2011

Accurate analysis of substrate sensitivity of active transistors in an analog circuit.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2009
A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009


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