Giorgio Spelgatti

According to our database, Giorgio Spelgatti authored at least 3 papers between 2010 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.

Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2013

A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS.

Francesco Radice, Melchiorre Bruccoleri, Marcello Ganzerli, Giorgio Spelgatti, Davide Sanzogni, Massimo Pozzoni, Andrea Mazzanti

Proceedings of the ESSCIRC 2013, 2013

2010

A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization.

Massimo Pozzoni, Simone Erba, Davide Sanzogni, Marcello Ganzerli, Paolo Viola, Daniele Baldi, Matteo Repossi, Giorgio Spelgatti, Francesco Svelto

Proceedings of the IEEE International Solid-State Circuits Conference, 2010