Sylvain Guilley
Orcid: 0000-0002-5044-3534Affiliations:
- Télécom Paris, Paris, France
According to our database1,
Sylvain Guilley
authored at least 301 papers
between 2004 and 2024.
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
Formal Security Proofs via Doeblin Coefficients: Optimal Side-channel Factorization from Noisy Leakage to Random Probing.
IACR Cryptol. ePrint Arch., 2024
Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generators.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024
2023
IEEE Trans. Computers, February, 2023
IEEE Trans. Computers, 2023
Exploiting the microarchitectural leakage of prefetching activities for side-channel attacks.
J. Syst. Archit., 2023
A masking method based on orthonormal spaces, protecting several bytes against both SCA and FIA with a reduced cost.
IACR Cryptol. ePrint Arch., 2023
IACR Cryptol. ePrint Arch., 2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the Advances in Information and Computer Security, 2023
Improved Alpha-Information Bounds for Higher-Order Masked Cryptographic Implementations.
Proceedings of the IEEE Information Theory Workshop, 2023
Proceedings of the IEEE International Symposium on Information Theory, 2023
Proceedings of the Progress in Cryptology - INDOCRYPT 2023, 2023
Challenges in generating true random numbers considering the variety of corners, aging, and attacks.
Proceedings of the International Conference on IC Design and Technology, 2023
Challenges in Generating True Random Numbers Considering the Variety of Corners, Aging, and Intentional Attacks.
Proceedings of the International Conference on IC Design and Technology, 2023
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2023
2022
Assessment and Mitigation of Power Side-Channel-Based Cross-PUF Attacks on Arbiter-PUFs and Their Derivatives.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Information Leakage in Code-Based Masking: A Systematic Evaluation by Higher-Order Attacks.
IEEE Trans. Inf. Forensics Secur., 2022
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Spectral approach to process the (multivariate) high-order template attack against any masking scheme.
J. Cryptogr. Eng., 2022
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Removing the Field Size Loss from Duc et al.'s Conjectured Bound for Masked Encodings.
IACR Cryptol. ePrint Arch., 2022
J. Electron. Test., 2022
Side-channel Analysis and Countermeasure for Implementation of Lattice-based Signature.
Proceedings of the 19th International Conference on Security and Cryptography, 2022
On the Practicality of Relying on Simulations in Different Abstraction Levels for Pre-silicon Side-Channel Analysis.
Proceedings of the 19th International Conference on Security and Cryptography, 2022
Proceedings of the IEEE International Symposium on Information Theory, 2022
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Quantifying the Speed-Up Offered by Genetic Algorithms during Fault Injection Cartographies.
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2022
Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure Chips.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 17th Canadian Workshop on Information Theory, 2022
Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, 2022
2021
Analysis of Multiplicative Low Entropy Masking Schemes Against Correlation Power Attack.
IEEE Trans. Inf. Forensics Secur., 2021
IEEE Trans. Inf. Forensics Secur., 2021
Intrinsic Resiliency of S-Boxes Against Side-Channel Attacks-Best and Worst Scenarios.
IEEE Trans. Inf. Forensics Secur., 2021
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021
Structural Attack (and Repair) of Diffused-Input-Blocked-Output White-Box Cryptography.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Stochastic methods defeat regular RSA exponentiation algorithms with combined blinding methods.
J. Math. Cryptol., 2021
J. Cryptogr. Eng., 2021
IACR Cryptol. ePrint Arch., 2021
J. Electron. Test., 2021
CoRR, 2021
Cryptogr. Commun., 2021
Proceedings of the IEEE Information Theory Workshop, 2021
Proceedings of the IEEE Information Theory Workshop, 2021
Proceedings of the IEEE International Symposium on Information Theory, 2021
Cumulant Expansion of Mutual Information for Quantifying Leakage of a Protected Secret.
Proceedings of the IEEE International Symposium on Information Theory, 2021
Proceedings of the 7th International Conference on Information Systems Security and Privacy, 2021
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level.
Proceedings of the IEEE European Symposium on Security and Privacy Workshops, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Enhancing the Resiliency of Multi-bit Parallel Arbiter-PUF and Its Derivatives Against Power Attacks.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2021
Proceedings of the Smart Card Research and Advanced Applications, 2021
Springer, ISBN: 978-3-030-77221-5, 2021
2020
IEEE Trans. Computers, 2020
J. Cryptogr. Eng., 2020
IACR Cryptol. ePrint Arch., 2020
Challenge codes for physically unclonable functions with Gaussian delays: A maximum entropy problem.
Adv. Math. Commun., 2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the IEEE International Test Conference, 2020
On-Chip Voltage and Temperature Digital Sensor for Security, Reliability, and Portability.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the IEEE European Test Symposium, 2020
PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community.
Proceedings of the IEEE European Test Symposium, 2020
Proceedings of the European Conference on Circuit Theory and Design, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020
Processor Anchor to Increase the Robustness Against Fault Injection and Cyber Attacks.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020
Proceedings of the ARES 2020: The 15th International Conference on Availability, 2020
2019
Proceedings of the Security and Privacy in the Internet of Things: Challenges and Solutions, 2019
Proceedings of the Security and Privacy in the Internet of Things: Challenges and Solutions, 2019
Best Information is Most Successful Mutual Information and Success Rate in Side-Channel Analysis.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019
IEEE Trans. Computers, 2019
Exhaustive single bit fault analysis. A use case against Mbedtls and OpenSSL's protection on ARM and Intel CPU.
Microprocess. Microsystems, 2019
J. Cryptogr. Eng., 2019
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019
Proceedings of the IEEE International Symposium on Information Theory, 2019
Proceedings of the Information Systems Security and Privacy - 5th International Conference, 2019
Proceedings of the 5th International Conference on Information Systems Security and Privacy, 2019
Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2019
Proceedings of the Codes, Cryptology and Information Security, 2019
Virtual Security Evaluation - An Operational Methodology for Side-Channel Leakage Detection at Source-Code Level.
Proceedings of the Codes, Cryptology and Information Security, 2019
2018
J. Hardw. Syst. Secur., 2018
On the Performance and Security of Multiplication in <i>GF</i>(2<sup><i>N</i></sup>).
Cryptogr., 2018
On the optimality and practicability of mutual information analysis in some scenarios.
Cryptogr. Commun., 2018
Statistical properties of side-channel and fault injection attacks using coding theory.
Cryptogr. Commun., 2018
Prediction-Based Intrusion Detection System for In-Vehicle Networks Using Supervised Learning and Outlier-Detection.
Proceedings of the Information Security Theory and Practice, 2018
Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2018
Development of the Unified Security Requirements of PUFs During the Standardization Process.
Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2018
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Confused yet Successful: - Theoretical Comparison of Distinguishers for Monobit Leakages in Terms of Confusion Coefficient and SNR.
Proceedings of the Information Security and Cryptology - 14th International Conference, 2018
Proceedings of the Cyber-Physical Systems Security., 2018
Proceedings of the Cyber-Physical Systems Security., 2018
Proceedings of the Cyber-Physical Systems Security., 2018
2017
IEEE Trans. Computers, 2017
J. Cryptogr. Eng., 2017
J. Cryptogr. Eng., 2017
IACR Cryptol. ePrint Arch., 2017
How Far Can We Reach? Breaking RSM-Masked AES-128 Implementation Using Only One Trace.
IACR Cryptol. ePrint Arch., 2017
Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the 2017 IEEE European Symposium on Security and Privacy, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Analyzing security breaches of countermeasures throughout the refinement process in hardware design flow.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017
Proceedings of the Smart Card Research and Advanced Applications, 2017
Proceedings of the Codes, Cryptology and Information Security, 2017
2016
Formally proved security of assembly code against power analysis - A case study on balanced logic.
J. Cryptogr. Eng., 2016
Method taking into account process dispersion to detect hardware Trojan Horse by side-channel analysis.
J. Cryptogr. Eng., 2016
IACR Cryptol. ePrint Arch., 2016
IACR Cryptol. ePrint Arch., 2016
Correlated Extra-Reductions Defeat Blinded Regular Exponentiation - Extended Version.
IACR Cryptol. ePrint Arch., 2016
IACR Cryptol. ePrint Arch., 2016
Evol. Comput., 2016
Adv. Math. Commun., 2016
Delay PUF Assessment Method Based on Side-Channel and Modeling Analyzes: The Final Piece of All-in-One Assessment Methodology.
Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016
Proceedings of the IEEE International Symposium on Information Theory, 2016
Proceedings of the IEEE International Symposium on Information Theory, 2016
Template Attacks with Partial Profiles and Dirichlet Priors: Application to Timing Attacks.
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2016
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2016, 2016
Proceedings of the New Codebreakers, 2016
Taylor Expansion of Maximum Likelihood Attacks for Masked and Shuffled Implementations.
Proceedings of the Advances in Cryptology - ASIACRYPT 2016, 2016
2015
ACM Trans. Reconfigurable Technol. Syst., 2015
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
IACR Cryptol. ePrint Arch., 2015
Evolutionary Approach for Finding Correlation Immune Boolean Functions of Order t with Minimal Hamming Weight.
Proceedings of the Theory and Practice of Natural Computing, 2015
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Exploiting small leakages in masks to turn a second-order attack into a first-order attack.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Multiply Constant-Weight Codes and the Reliability of Loop Physically Unclonable Functions.
IEEE Trans. Inf. Theory, 2014
J. Math. Cryptol., 2014
J. Cryptogr. Eng., 2014
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest.
J. Cryptogr. Eng., 2014
J. Cryptogr. Eng., 2014
Attacking Suggest Boxes in Web Applications Over HTTPS Using Side-Channel Stochastic Algorithms.
IACR Cryptol. ePrint Arch., 2014
IACR Cryptol. ePrint Arch., 2014
IACR Cryptol. ePrint Arch., 2014
A Theoretical Study of Kolmogorov-Smirnov Distinguishers: Side-Channel Analysis vs. Differential Cryptanalysis.
IACR Cryptol. ePrint Arch., 2014
IACR Cryptol. ePrint Arch., 2014
Orthogonal Direct Sum Masking: A Smartcard Friendly Computation Paradigm in a Code, with Builtin Protection against Side-Channel and Fault Attacks.
IACR Cryptol. ePrint Arch., 2014
IACR Cryptol. ePrint Arch., 2014
Proceedings of the Information Security Theory and Practice. Securing the Internet of Things, 2014
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2014
Formal Analysis of CRT-RSA Vigilant's Countermeasure Against the BellCoRe Attack: A Pledge for Formal Methods in the Field of Implementation Security.
Proceedings of the 3rd ACM SIGPLAN Program Protection and Reverse Engineering Workshop 2014, 2014
Hardware-enforced Protection against Software Reverse-Engineering based on an Instruction Set Encoding.
Proceedings of the 3rd ACM SIGPLAN Program Protection and Reverse Engineering Workshop 2014, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the First Workshop on Cryptography and Security in Computing Systems, 2014
Encoding the state of integrated circuits: a proactive and reactive protection against hardware Trojans horses.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014
Proceedings of the Progress in Cryptology - AFRICACRYPT 2014, 2014
Proceedings of the 4th Program Protection and Reverse Engineering Workshop, 2014
2013
J. Cryptogr. Eng., 2013
J. Cryptogr. Eng., 2013
From cryptography to hardware: analyzing and protecting embedded Xilinx BRAM for cryptographic applications.
J. Cryptogr. Eng., 2013
IACR Cryptol. ePrint Arch., 2013
IACR Cryptol. ePrint Arch., 2013
IACR Cryptol. ePrint Arch., 2013
IACR Cryptol. ePrint Arch., 2013
Theory of masking with codewords in hardware: low-weight <i>d</i>th-order correlation-immune Boolean functions.
IACR Cryptol. ePrint Arch., 2013
Proceedings of the 2013 IEEE International Symposium on Information Theory, 2013
Proceedings of the Foundations and Practice of Security - 6th International Symposium, 2013
Proceedings of the Foundations and Practice of Security - 6th International Symposium, 2013
A low-entropy first-degree secure provable masking scheme for resource-constrained devices.
Proceedings of the Workshop on Embedded Systems Security, 2013
2012
Proceedings of the Fault Analysis in Cryptography, 2012
Int. J. Reconfigurable Comput., 2012
IACR Cryptol. ePrint Arch., 2012
Proceedings of the Information Security Theory and Practice. Security, Privacy and Trust in Computing Systems and Ambient Intelligent Ecosystems, 2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Proceedings of the Information Systems, Technology and Management, 2012
Proceedings of the Information and Communications Security - 14th International Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012
Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27, 2012
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012
Proceedings of the Smart Card Research and Advanced Applications, 2012
Protection des Accélérateurs Matériels de Cryptographie Symétrique. (Protection of Symmetric Cryptography Hardware Accelerators).
, 2012
2011
Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks.
IET Inf. Secur., 2011
Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks.
IACR Cryptol. ePrint Arch., 2011
Classification of High-Order Boolean Masking Schemes and Improvements of their Efficiency.
IACR Cryptol. ePrint Arch., 2011
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback
CoRR, 2011
Proceedings of the Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication, 2011
Proceedings of the Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication, 2011
Proceedings of the Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication, 2011
Proceedings of the 2011 IEEE International Workshop on Information Forensics and Security, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the Security Aspects in Information Technology, 2011
Proceedings of the HOST 2011, 2011
Proceedings of the HOST 2011, 2011
Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
2010
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics.
IEEE Trans. Computers, 2010
Int. J. Reconfigurable Comput., 2010
Practical Improvements of Profiled Side-Channel Attacks on a Hardware Crypto-Accelerator.
IACR Cryptol. ePrint Arch., 2010
Proceedings of the Information Security Applications - 11th International Workshop, 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the Progress in Cryptology, 2010
Proceedings of the Information Security and Cryptology - ICISC 2010, 2010
Proceedings of the IEEE International Conference on Acoustics, 2010
Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2010
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks.
Proceedings of the Topics in Cryptology, 2010
Proceedings of the Information Security and Cryptology - 6th International Conference, 2010
Proceedings of the 5th Workshop on Embedded Systems Security, 2010
2009
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.
ACM Trans. Reconfigurable Technol. Syst., 2009
Microelectron. J., 2009
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009
Proceedings of the Sixth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2009
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the The Forth International Conference on Availability, 2009
2008
IEEE Trans. Computers, 2008
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks
CoRR, 2008
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.
Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008
Proceedings of the NTMS 2008, 2008
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.
Proceedings of the FPL 2008, 2008
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008
Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008
Proceedings of the Seventh European Dependable Computing Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
Integr., 2007
IEEE Des. Test Comput., 2007
Towards Quantum Key Distribution System using Homodyne Detection with Differential Time-Multiplexed Reference.
Proceedings of the 2007 IEEE International Conference on Research, 2007
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
Proceedings of the FPL 2007, 2007
2006
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006
2005
The Proof by 2M-1: a Low-Cost Method to Check Arithmetic Computations.
Proceedings of the Security and Privacy in the Age of Ubiquitous Computing, IFIP TC11 20th International Conference on Information Security (SEC 2005), May 30, 2005
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005
2004
Proceedings of the Smart Card Research and Advanced Applications VI, 2004