David L. Landis

According to our database, David L. Landis authored at least 28 papers between 1987 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Targeted random test generation for power-aware multicore designs.

Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis

ACM Trans. Design Autom. Electr. Syst., 2012

Hazard driven test generation for SMT processors.

Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2010

Test Generation for CMP Designs.

Padmaraj Singh, David L. Landis

Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

2009

Test Generation for Precise Interrupts on Out-of-Order Microprocessors.

Padmaraj Singh, David L. Landis, Vijaykrishnan Narayanan

Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

2003

The Sandbox Design Experience Course.

Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Microelectronics Education As Workforce Development.

David L. Landis, James T. Cain

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Short Courses in System-on-a-Chip (SoC) Design.

Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

2000

Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits.

Bassam Shaer, David L. Landis, Sami A. Al-Arian

IEEE Trans. Very Large Scale Integr. Syst., 2000

Partitioning sequential circuits for pseudoexhaustive testing.

Bassam Shaer, Sami A. Al-Arian, David L. Landis

IEEE Trans. Very Large Scale Integr. Syst., 2000

1999

Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use.

David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor

Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

A Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems.

Scott Deno, David L. Landis, Paul T. Hulina, Sanjay Balasubramanian

Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Computing in Memory Architectures for Digital Image Processing.

Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno

Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

Using RASSP Modules in a Rapid System Prototyping Class.

David L. Landis

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

Evaluation of Computing in Memory Architectures for Digital Image Processing Applications.

David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor

Proceedings of the IEEE International Conference On Computer Design, 1999

Pseudo-Exhaustive Testing of Sequential Circuits.

Bassam Shaer, Sami A. Al-Arian, David L. Landis

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

Partitioning algorithm to enhance VLSI testability.

Bassam Shaer, Sami A. Al-Arian, David L. Landis

Proceedings of the 36th Annual ACM Southeast Regional Conference, 1998

1997

A WWW facilitated rapid system prototyping class.

David L. Landis, Paul T. Hulina

Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

An electronics manufacturing minor in engineering with emphasis on rapid prototyping.

Paul T. Hulina, David L. Landis

Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

1996

A novel built-in current sensor for I_DDQ testing of deep submicron CMOS ICs.

Stephan P. Athan, David L. Landis, Sami A. Al-Arian

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1992

A test methodology for wafer scale system.

David L. Landis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Wafer-Scale Optimization Using Computational Availability.

David L. Landis, Nitin Nigam, Joseph W. Yoder

Computer, 1992

Applications of the IEEE P1149.5 Module Test and Maintenance Bus.

David L. Landis, Chuck Hudson, Patrick F. McHugh

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

Wafer Scale Integration: A university perspective.

Vijay K. Jain, David L. Landis, David C. Keezer, K. T. Wilson, Denny Whittaker

J. VLSI Signal Process., 1991

1990

Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration.

David L. Landis, Padmaraj Singh

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989

A Self-Test System Architecture for Reconfigurable WSI.

David L. Landis

Proceedings of the Proceedings International Test Conference 1989, 1989

Systolic L-U decomposition array with a new reciprocal cell.

Vijay K. Jain, David L. Landis, C. E. Alvarez

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988

Evaluation of System BIST Using Computational Performance Measures.

David L. Landis, Daniel C. Muha

Proceedings of the Proceedings International Test Conference 1988, 1988

1987

Influence of Built-In Self Test on the Performance of Fault Tolerant VLSI Multiprocessors.

David L. Landis, Daniel C. Muha, William A. Check

Proceedings of the International Conference on Parallel Processing, 1987