Davide Sabena
According to our database1,
Davide Sabena
authored at least 17 papers
between 2011 and 2022.
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Bibliography
2022
IEEE Syst. J., 2022
2015
New Test and Fault Tolerance Techniques for Reliability Characterization of Parallel and Reconfigurable Processors.
PhD thesis, 2015
2014
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results.
Microelectron. Reliab., 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Reconfigurable high performance architectures: How much are they ready for safety-critical applications?
Proceedings of the 19th IEEE European Test Symposium, 2014
2013
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
On the optimized generation of Software-Based Self-Test programs for VLIW processors.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 20th Euromicro International Conference on Parallel, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011