Mario Schölzel
According to our database1,
Mario Schölzel
authored at least 50 papers
between 2005 and 2023.
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Bibliography
2023
Coarse-grained Control Flow Integrity Check for Processors with Sliding Register Windows.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023
2022
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022
Combination of ROP Defense Mechanisms for Better Safety and Security in Embedded Systems.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
2020
2019
M2-DaGNoS: A data gathering and node scheduling mechanism for Multimodal Wireless Sensor Networks.
Comput. Commun., 2019
2018
Handling of transient and permanent faults in dynamically scheduled super-scalar processors.
Microelectron. Reliab., 2018
A fault tolerant dynamically scheduled processor with partial permanent fault handling.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
2017
WISDOM - A wireless debugging and power measurement system for field tests and device observation in WSN.
Proceedings of the Signal Processing: Algorithms, 2017
Outdoor Range Measurements in Sub-GHz License-free Radio Bands under Realistic Conditions.
Proceedings of the 15th ACM International Symposium on Mobility Management and Wireless Access, 2017
Handling manufacturing and aging faults with software-based techniques in tiny embedded systems.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017
2016
Non-Cyclic Design Space Exploration for ASIPs - Compiler-Centered Microprocessor Design (CoMet).
J. Circuits Syst. Comput., 2016
A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors.
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
2015
A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems.
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the 10th International Design & Test Symposium, 2015
Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015
Softwarebasierte Fehlertolerenz für Flash-Speicher von mikrocontroller-basierten Systemen.
Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015
Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen.
Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIP.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
Vergleich der Beschreibung und Simulation einer Befehlssatzarchitektur in LISA und CoMet.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
Systematic generation of diagnostic software-based self-test routines for processor components.
Proceedings of the 19th IEEE European Test Symposium, 2014
Reconfigurable high performance architectures: How much are they ready for safety-critical applications?
Proceedings of the 19th IEEE European Test Symposium, 2014
Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
2013
Towards a Graceful Degradable Multicore-System by Hierarchical Handling of Hard Errors.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013
Ein konfigurierbarer Zwischencodesimulator zum compilerzentrierten Mikroprozessorentwurf.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
Towards an automatic generation of diagnostic in-field SBST for processor components.
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
2012
An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Hierarchical Self-repair in Heterogeneous Multi-core Systems by Means of a Software-based Reconfiguration.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
Combining Hardware- and Software-Based Self-Repair Methods for Statically Scheduled Data Paths.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data paths.
Proceedings of the Design, Automation and Test in Europe, 2010
2008
Automatic Generation of Cycle Accurate SystemC Models for Application Specific Clustered VLIW Processors.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008
2007
Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Zeitbeschränkte Clusterung zur Design-Space-Exploration geclusterter VLIW-Prozessoren.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006
2005
Proceedings of the Systems Aspects in Organic and Pervasive Computing, 2005