Deepak Kamalanathan

According to our database, Deepak Kamalanathan authored at least 4 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing.

Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Wei D. Lu, Zhengya Zhang, Michael P. Flynn

IEEE J. Solid State Circuits, August, 2025

2024

Self-rectifying non-volatile tunneling synapse: multiscale modeling augmented development.

Bastien Beltrando, Marco A. Villena, Mondol Anik Kumar, Shruba Gangopadhyay, Deepak Kamalanathan, E. Smith, Nasrin Kazem, Ghazal Saheli, Stephen Weeks, Michael Haverty, Muthukumar Kaliappan, Andrea Padovani, S. Krishnan, Jeffrey W. Anthis, Luca Larcher, Milan Pesic

Proceedings of the IEEE International Memory Workshop, 2024

2022

A Fully Integrated System-on-Chip Design with Scalable Resistive Random-Access Memory Tile Design for Analog in-Memory Computing.

Fuxi Cai, She-Hwa Yen, Apurva Uppala, Luke Thomas, Tianchi Liu, Peter Fu, Xiaofeng Zhang, Ambrose Low, Deepak Kamalanathan, Joe Hsu, Buvna Ayyagari-Sangamalli

Adv. Intell. Syst., 2022

An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine.

Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Zhengya Zhang, Wei D. Lu, Michael P. Flynn

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022