Dimitris Agiakatsikas

Orcid: 0000-0001-8849-8074

According to our database1, Dimitris Agiakatsikas authored at least 19 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Single Event Effects Assessment of UltraScale+ MPSoC Systems Under Atmospheric Radiation.
IEEE Trans. Reliab., March, 2024

2023
A Methodology for Fault-tolerant Pareto-optimal Approximate Designs of FPGA-based Accelerators.
ACM Trans. Embed. Comput. Syst., July, 2023

Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Detecting Hardware Faults in Approximate Adders via Minimum Redundancy.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

2022
Evaluation of Xilinx Deep Learning Processing Unit under Neutron Irradiation.
CoRR, 2022

The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based Neural Networks.
Proceedings of the International Conference on Field-Programmable Technology, 2022

2019
High-level synthesis of triple modular redundant FPGA circuits with energy efficient error recovery mechanisms.
PhD thesis, 2019

2018
Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems.
ACM Trans. Reconfigurable Technol. Syst., 2018

FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs.
IEEE Trans. Aerosp. Electron. Syst., 2018

Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery.
Microprocess. Microsystems, 2018

From C to Fault-Tolerant FPGA-Based Systems.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
Reliable SEU monitoring and recovery using a programmable configuration controller.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016
Fine-grained module-based error recovery in FPGA-based TMR systems.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Dynamic scheduling of voter checks in FPGA-based TMR systems.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A Programmable Configuration Controller for fault-tolerant applications.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Reconfiguration Control Networks for TMR Systems with Module-Based Recovery.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2014
A soft error vulnerability analysis framework for Xilinx FPGAs.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014


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