Nikos Foutris

Orcid: 0000-0003-1691-968X

According to our database1, Nikos Foutris authored at least 29 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Single Event Effects Assessment of UltraScale+ MPSoC Systems Under Atmospheric Radiation.
IEEE Trans. Reliab., March, 2024

2023
TornadoQSim: An Open-source High-Performance and Modular Quantum Circuit Simulation Framework.
CoRR, 2023

Experiences in Building a Composable and Functional API for Runtime SPIR-V Code Generation.
CoRR, 2023

Beehive SPIR-V Toolkit: A Composable and Functional API for Runtime SPIR-V Code Generation.
Proceedings of the 15th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages, 2023

A Multifaceted Memory Analysis of Java Benchmarks.
Proceedings of the 20th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes, 2023

Scaling Up Performance of Managed Applications on NUMA Systems.
Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management, 2023

2022
Evaluation of Xilinx Deep Learning Processing Unit under Neutron Irradiation.
CoRR, 2022

2020
Transparent acceleration of Java-based deep learning engines.
Proceedings of the MPLR '20: 17th International Conference on Managed Programming Languages and Runtimes, 2020

You can't hide you can't run: a performance assessment of managed applications on a NUMA machine.
Proceedings of the MPLR '20: 17th International Conference on Managed Programming Languages and Runtimes, 2020

2019
Demystifying Crypto-Mining: Analysis and Optimizations of Memory-Hard PoW Algorithms.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Simulating Wear-out Effects of Asymmetric Multicores at the Architecture Level.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
On the future of research VMs: a hardware/software perspective.
Proceedings of the Conference Companion of the 2nd International Conference on Art, 2018

2017
Experiences with Building Domain-Specific Compilation Plugins in Graal.
Proceedings of the 14th International Conference on Managed Languages and Runtimes, 2017

Cross-ISA debugging in meta-circular VMs.
Proceedings of the 9th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages, Vancouver, BC, Canada, October 23, 2017


2016
Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Faults in data prefetchers: Performance degradation and variability.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2015
Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.
Microprocess. Microsystems, 2015

Bayesian network early reliability evaluation analysis for both permanent and transient faults.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Differential Fault Injection on Microarchitectural Simulators.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

A Bayesian model for system level reliability estimation.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
Accelerated online error detection in many-core microprocessor architectures.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Versatile architecture-level fault injection framework for reliability evaluation: A first report.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013
Deconfigurable microprocessor architectures for silicon debug acceleration.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Online error detection in multiprocessor chips: A test scheduling study.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Measuring the performance impact of permanent faults in modern microprocessor architectures.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Assessing the impact of hard faults in performance components of modern microprocessors.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2011
Accelerating microprocessor silicon validation by exposing ISA diversity.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

2010
MT-SBST: Self-test optimization in multithreaded multicore architectures.
Proceedings of the 2011 IEEE International Test Conference, 2010


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