Oliver Diessel

According to our database1, Oliver Diessel authored at least 61 papers between 1996 and 2019.

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Bibliography

2019
Efficient Fine-grained Processor-logic Interactions on the Cache-coherent Zynq Platform.
TRETS, 2019

Scheduling configuration memory error checks to improve the reliability of FPGA-based systems.
IET Computers & Digital Techniques, 2019

Introduction to RAW 2019.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2018
Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems.
TRETS, 2018

Fault Recovery Time Analysis for Coarse-Grained Reconfigurable Architectures.
ACM Trans. Embedded Comput. Syst., 2018

FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs.
IEEE Trans. Aerospace and Electronic Systems, 2018

Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

A Short-Transfer Model for Tightly-Coupled CPU-FPGA Platforms.
Proceedings of the International Conference on Field-Programmable Technology, 2018

From C to Fault-Tolerant FPGA-Based Systems.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
The First 25 Years of the FPL Conference: Significant Papers.
TRETS, 2017

Service-Oriented Architecture on FPGA-Based MPSoC.
IEEE Trans. Parallel Distrib. Syst., 2017

Reliable SEU monitoring and recovery using a programmable configuration controller.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Scheduling Considerations for Voter Checking in TMR-MER Systems.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Fine-grained module-based error recovery in FPGA-based TMR systems.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Dynamic scheduling of voter checks in FPGA-based TMR systems.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A Programmable Configuration Controller for fault-tolerant applications.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Reconfiguration Control Networks for TMR Systems with Module-Based Recovery.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
A programmable multi-GNSS baseband receiver.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Improving Fmax of FPGA circuits employing DPR to recover from configuration memory upsets.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Significant papers from the first 25 years of the FPL conference.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Simulation-based functional verification of dynamically reconfigurable systems.
ACM Trans. Embedded Comput. Syst., 2014

Reconfiguration network design for SEU recovery in FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Guest Editorial: Field-Programmable Technology.
Signal Processing Systems, 2012

Functionally verifying state saving and restoration in dynamically reconfigurable systems.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011
ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration.
TRETS, 2010

FPGA-based video processing for a vision prosthesis.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Towards Dilated Placement of Dynamic NoC Cores.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

2008
ACS: An Addressless Configuration Support for efficient partial reconfigurations.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices.
Proceedings of the FPL 2007, 2007

2006
Communications infrastructure generation for modular FPGA reconfiguration.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

The Entropy of FPGA Reconfiguration.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Enabling RTR for industry.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs.
Proceedings of the ARCS 2006, 2006

Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
FPGA implementation of population-based ant colony optimization.
Appl. Soft Comput., 2004

On the placement and granularity of FPGA configurations.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

2002
An FPGA Interpreter with Virtual Hardware Management.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Resource-aware run-time elaboration of behavioural FPGA specifications.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Population based ant colony optimization on FPGA.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs (Research Note).
Proceedings of the Euro-Par 2002, 2002

2001
On Dynamic Task Scheduling for EPGA-Based Systems.
Int. J. Found. Comput. Sci., 2001

Chip-Based Reconfigurable Task Management.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
Configurable Architectures Workshop (RAW 2000).
Proceedings of the Parallel and Distributed Processing, 2000

Compiling Process Algebraic Descriptions into Reconfigurable Logic.
Proceedings of the Parallel and Distributed Processing, 2000

Behavioural Language Compilation with Virtual Hardware Management.
Proceedings of the Field-Programmable Logic and Applications, 2000

1999
A Web-Based Multiuser Operating System for Reconfiguarble Computing.
Proceedings of the Parallel and Distributed Processing, 1999

1998
Partial Rearrangements of Space-Shared FPGAs.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

Partial FPGA Rearrangement by Local Repacking (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997
Run-time compaction of FPGA designs.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

1996
Optimal Algorithms for Constrained Reconfigurable Meshes.
J. Parallel Distrib. Comput., 1996


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