Dinesh Patil

According to our database, Dinesh Patil authored at least 13 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2023

A prototype 5nm custom sensor SoC for Augmented Reality/Virtual Reality targeting Smartglasses with embedded computer vision, audio, security and ML.

Karl Kaiser, Dinesh Patil, Edith Beigné

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2019

The impact of colleges and hospitals to local real estate markets.

Ryan Rivas, Dinesh Patil, Vagelis Hristidis, Joseph R. Barr, Narayanan Srinivasan

J. Big Data, 2019

2012

10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS.

Frankie Liu, Dinesh Patil, Jon K. Lexau, Philip Amberg, Michael Dayringer, Jonathan Gainsley, Hesam Fathi Moghadam, Xuezhe Zheng, John E. Cunningham, Ashok V. Krishnamoorthy, Elad Alon, Ron Ho

IEEE J. Solid State Circuits, 2012

2011

Digitally-assisted analog circuits for a 10 Gbps, 395 fJ/b optical receiver in 40 nm CMOS.

Philip Amberg, Frankie Liu, Michael Dayringer, Jon K. Lexau, Dinesh Patil, Jonathan Gainsley, Hesam Fathi Moghadam, Elad Alon, Xuezhe Zheng, John E. Cunningham, Ashok V. Krishnamoorthy, Ron Ho

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

Optical Interconnect for High-End Computer Systems.

Ron Ho, Frankie Liu, Dinesh Patil, Xuezhe Zheng, Guoliang Li, Ivan Shubin, Elad Alon, Jon K. Lexau, Herb Schwetman, John E. Cunningham, Ashok V. Krishnamoorthy

IEEE Des. Test Comput., 2010

Clocking Links in Multi-chip Packages: A Case Study.

Tamer A. Ali, Dinesh Patil, Frankie Liu, Elad Alon, Jon K. Lexau, Chih-Kong Ken Yang, Ron Ho

Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010

Probe station selection algorithms for fault management in computer networks.

Deepak Jeswani, Nakul Korde, Dinesh Patil, Maitreya Natu, John Augustine

Proceedings of the Second International Conference on Communication Systems and Networks, 2010

2008

Processor Performance Modeling using Symbolic Simulation.

Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang, Mark Horowitz

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

Energy-delay tradeoffs in 32-bit static shifter designs.

Steven Huntzicker, Michael Dayringer, Justin Soprano, Anthony Weerasinghe, David Money Harris, Dinesh Patil

Proceedings of the 26th International Conference on Computer Design, 2008

2007

Robust Energy-Efficient Adder Topologies.

Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman

Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2005

Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS.

Ken Mai, Ron Ho, Elad Alon, Dean Liu, Younggon Kim, Dinesh Patil, Mark A. Horowitz

IEEE J. Solid State Circuits, 2005

Digital Circuit Optimization via Geometric Programming.

Stephen P. Boyd, Seung-Jean Kim, Dinesh Patil, Mark Horowitz

Oper. Res., 2005

A New Method for Design of Robust Digital Circuits.

Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005