Dominic DiClemente

According to our database, Dominic DiClemente authored at least 6 papers between 2007 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS.

Ravi Shivnaraine, Marcus van Ierssel, Kamran Farzan, Dominic DiClemente, George Ng, Nanyan Wang, Javid Musayev, Gairik Dutta, Masumi Shibata, Arash Moradi, Haleh Vahedi, Manavi Farzad, Prabhnoor Kainth, Matt Yu, Nhat Nguyen, Jennifer Pham, Angus McLaren

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2018

A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support.

Mohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus McLaren, Jennifer Pham, Kamran Farzan, Dominic DiClemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris D. Holdenried, Saman Sadr

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2009

A Wide Frequency Tuning Range Active-inductor Voltage-controlled Oscillator for Ultra Wideband Applications.

Dominic DiClemente, Fei Yuan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Current-Mode Phase-Locked Loops With CMOS Active Transformers.

Dominic DiClemente, Fei Yuan, Adrian Tang

IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007

Current-Mode Phase-Locked Loops - A New Architecture.

Dominic DiClemente, Fei Yuan

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Current-Mode Phase-Locked Loops with Low Supply Voltage Sensitivity.

Dominic DiClemente, Fei Yuan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007