Jennifer Pham

According to our database1, Jennifer Pham authored at least 4 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2018
A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2011
An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2008
A Time-Interleaved DeltaSigma-DAC Architecture Clocked at the Nyquist Rate.
IEEE Trans. Circuits Syst. II Express Briefs, 2008


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