Mohammad Sadegh Jalali

According to our database1, Mohammad Sadegh Jalali authored at least 11 papers between 2010 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
High speed ADCs for wireline applications.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2015
A 3x blind ADC-based CDR for a 20 dB loss channel.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs.
IEEE J. Solid State Circuits, 2015

A Reference-Less Single-Loop Half-Rate Binary CDR.
IEEE J. Solid State Circuits, 2015

2014
An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset".
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs.
Proceedings of the Symposium on VLSI Circuits, 2014

A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011
A hybrid phase-locked loop for CDR Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
An RF power harvesting system with input-tuning for long-range RFID tags.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010


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