Chris D. Holdenried

According to our database1, Chris D. Holdenried authored at least 5 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2014
Performance of edge tap decision feedback equalization methods for wireline receivers.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Test considerations for jitter tolerance of wireline receivers.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

2011
An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2004
A DC-6 GHz, 50 dB dynamic range, SiGe HBT true logarithmic amplifier.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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