Kamran Farzan

According to our database1, Kamran Farzan authored at least 8 papers between 2003 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2018
A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2012
A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2008
A Robust 4-PAM Signaling Scheme for Inter-Chip Links Using Coding in Space.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2006
Coding schemes for chip-to-chip interconnect applications.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2004
A low-power crosstalk-insensitive signaling scheme for chip-to-chip communication.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A low-complexity power-efficient signaling scheme for chip-to-chip communication.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A power-efficient architecture for high-speed D/A converters.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


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