Ravi Shivnaraine

According to our database, Ravi Shivnaraine authored at least 5 papers between 2011 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 0.23pJ/b 24Gb/s Modular D2D Interface with Zero Wake Penalty Clock Gating in 3nm.

Ravi Shivnaraine, Charles Boecker, Eric Groen, Simon Li, Ping Lu, Socrates D. Vamvakos, Roxanne Vu, Chris Hanke, Shankar Tangirala, Wen Liu, Marina Salik, Kevin Bartholomew, Sushmitha Reddy, Alex Tessitore, Aws Shallal, Kalyan Nallaparaju, Jin Liang, Minhan Chen, Shaishav Desai

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2021

11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS.

Ravi Shivnaraine, Marcus van Ierssel, Kamran Farzan, Dominic DiClemente, George Ng, Nanyan Wang, Javid Musayev, Gairik Dutta, Masumi Shibata, Arash Moradi, Haleh Vahedi, Manavi Farzad, Prabhnoor Kainth, Matt Yu, Nhat Nguyen, Jennifer Pham, Angus McLaren

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2014

An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset".

Ravi Shivnaraine, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection.

Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011

A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS.

Behrooz Abiri, Ravi Shivnaraine, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune

Proceedings of the IEEE International Solid-State Circuits Conference, 2011