Dongjun Park

According to our database, Dongjun Park authored at least 12 papers between 2017 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Stealing Keys From Hardware Wallets: A Single Trace Side-Channel Attack on Elliptic Curve Scalar Multiplication Without Profiling.

Dongjun Park, Minsig Choi, GyuSang Kim, Daehyeon Bae, Heeseok Kim, Seokhie Hong

IEEE Access, 2023

Autoscaled-Wavelet Convolutional Layer for Deep Learning-Based Side-Channel Analysis.

Daehyeon Bae, Dongjun Park, GyuSang Kim, Minsig Choi, Nayeon Lee, Heeseok Kim, Seokhie Hong

IEEE Access, 2023

2021

Single trace side-channel attack on key reconciliation in quantum key distribution system and its efficient countermeasures.

Dongjun Park, GyuSang Kim, Donghoe Heo, Suhri Kim, HeeSeok Kim, Seokhie Hong

ICT Express, 2021

Structured Pattern Pruning Using Regularization.

Dongjun Park, Geung-Hee Lee

CoRR, 2021

Workspace Derivation of Arthroscope Using Morphological Data and Standard Portal Placement Method for Shoulder Arthroscopy.

Chang-Kyun Kim, Joonhwan Kim, Dongjun Park, Dong-Soo Kwon

IEEE Access, 2021

Side Channel Vulnerability in Parity Computation of Generic Key Reconciliation Process on QKD.

GyuSang Kim, Dongjun Park, HeeSeok Kim, Seokhie Hong

Proceedings of the International Conference on Information and Communication Technology Convergence, 2021

2020

A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication.

Dongjun Park, Jongsun Kim

IEICE Electron. Express, 2020

A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL.

Dongjun Park, Jongsun Kim

Circuits Syst. Signal Process., 2020

Single Trace Attack on Key Reconciliation Process for Quantum Key Distribution.

Dongjun Park, Donghoe Heo, Suhri Kim, Seokhie Hong

Proceedings of the International Conference on Information and Communication Technology Convergence, 2020

2018

A 7-GHz Fast-Lock 2-Step TDC-based All-Digital DLL for Post-DDR4 SDRAMs.

Dongjun Park, Jongsun Kim

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A 0.15 to 2.2 GHz all-digital delay-locked loop.

Dongjun Park, Geontae Park, Jongsun Kim

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A low-power SerDes for high-speed on-chip networks.

Dongjun Park, Junsub Yoon, Jongsun Kim

Proceedings of the International SoC Design Conference, 2017