Junsub Yoon

According to our database¹, Junsub Yoon authored at least 6 papers between 2016 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Bibliography

2024

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5<sup>th</sup>-Generation 10nm DRAM Process.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021

A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM.

[BibT_eX]

[DOI]

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2017

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs.

[BibT_eX]

[DOI]

Junsub Yoon

Seo Weon Heo

Jongsun Kim

IEICE Electron. Express, 2017

A low-power SerDes for high-speed on-chip networks.

[BibT_eX]

[DOI]

Dongjun Park

Junsub Yoon

Jongsun Kim

Proceedings of the International SoC Design Conference, 2017

2016

A MDLL-based multi-phase clock multiplier.

[BibT_eX]

[DOI]

Junsub Yoon

Jongsun Kim

Proceedings of the International SoC Design Conference, 2016

Junsub Yoon

Timeline

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