Chiweon Yoon
Orcid: 0000-0002-3786-8079Affiliations:
- Samsung Electronics, Hwasung, South Korea
- Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea (former, PhD 2004)
According to our database1,
Chiweon Yoon authored at least 18 papers
between 2001 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2026
A 28-Gb/mm<sup>2</sup> 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs.
IEEE J. Solid State Circuits, January, 2026
37.7 A 12.8Gb/s Parallel Receiver with a One-Way Self-Training Scheme for Equalizing ISI and Reflections in Multi-Drop Memory Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 0.87pJ/b 17Gb/s/pin Parallel Receiver with a Local DQS Recovery for a Supply-Noise-Tolerant DQS Distribution in High-Performance NAND Flash Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
30.1 A 28Gb/mm<sup>2</sup>4XX-Layer 1Tb 3b/Cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/Pin IOs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2023
A 3.0 Gb/s/pin 4<sup>th</sup> generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Integrated Circuit to Compensate Parasitic Leakage Component for WL Leakage Current in NAND Flash Memory.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage.
IEEE J. Solid State Circuits, 2021
A 512Gb 3b/Cell 7<sup>th</sup> -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
A Hybrid ZQ Calibration Design for High-Density Flash Memory Toggle 5.0 High-speed Interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 512Gb 3-bit/Cell 3D 6<sup>th</sup>-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2005
2002
A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip.
IEEE J. Solid State Circuits, 2002
2001
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications.
IEEE J. Solid State Circuits, 2001
A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001