Eduardo Luis Rhod

According to our database1, Eduardo Luis Rhod authored at least 11 papers between 2003 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
A new structure of UHF RFID tag antenna mountable on metallic surface using double slits.
Proceedings of the 9th IEEE Latin-American Conference on Communications, 2017

2010
A New Soft-Error Resilient Voltage-Mode Quaternary Latch.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A new RC design for mixed-grain based dynamically reconfigurable architectures.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs.
J. Electron. Test., 2008

An efficient test and characterization approach for nanowire-based architectures.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Binary translation process to optimize nanowire arrays usage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A low-SER efficient core processor architecture for future technologies.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Using Memory to Cope with Simultaneous Transient Faults.
Proceedings of the 7th Latin American Test Workshop, 2006

2004
Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems.
J. Electron. Test., 2004

2003
Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy?
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003


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