Fateme S. Hosseini

Orcid: 0000-0002-9091-3908

According to our database1, Fateme S. Hosseini authored at least 10 papers between 2017 and 2021.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation.
ACM Trans. Embed. Comput. Syst., 2021

A Compile-Time Framework for Tolerating Read Disturbance in STT-RAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Safeguarding the Intelligence of Neural Networks with Built-in Light-weight Integrity MArks (LIMA).
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

A Self-Test Framework for Detecting Fault-induced Accuracy Drop in Neural Network Accelerators.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Trustworthy AI Inference Systems: An Industry Research View.
CoRR, 2020

2019
Comprehensive Evaluation of Program Reliability with ComFIDet: An Integrated Fault Injection and Detection Framework for Embedded Systems.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

Compiler-Directed and Architecture-Independent Mitigation of Read Disturbance Errors in STT-RAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Low Overhead Solution to Resilient Assembly Lines Built From Legacy Controllers.
IEEE Embed. Syst. Lett., 2018

2017
Segment and Conflict Aware Page Allocation and Migration in DRAM-PCM Hybrid Main Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Leveraging Compiler Optimizations to Reduce Runtime Fault Recovery Overhead.
Proceedings of the 54th Annual Design Automation Conference, 2017


  Loading...