Saransh Gupta

Orcid: 0000-0001-5814-3934

According to our database1, Saransh Gupta authored at least 49 papers between 2017 and 2024.

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Bibliography

2024
MemFHE: End-to-end Computing with Fully Homomorphic Encryption in Memory.
ACM Trans. Embed. Comput. Syst., March, 2024

2023
ClotCatcher: a novel natural language model to accurately adjudicate venous thromboembolism from radiology reports.
BMC Medical Informatics Decis. Mak., December, 2023

RAPIDx: High-Performance ReRAM Processing In-Memory Accelerator for Sequence Alignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

FHEmem: A Processing In-Memory Accelerator for Fully Homomorphic Encryption.
CoRR, 2023

Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Efficient Machine Learning on Encrypted Data Using Hyperdimensional Computing.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Enhanced Heart Disease Classification Using Parallelization and Integrated Machine-Learning Techniques.
Proceedings of the Computer Vision and Image Processing - 8th International Conference, 2023

2022
Integrative Network Modeling Highlights the Crucial Roles of Rho-GDI Signaling Pathway in the Progression of non-Small Cell Lung Cancer.
IEEE J. Biomed. Health Informatics, 2022

Store-n-Learn: Classification and Clustering with Hyperdimensional Computing across Flash Hierarchy.
ACM Trans. Embed. Comput. Syst., 2022

COSMO: Computing with Stochastic Numbers in Memory.
ACM J. Emerg. Technol. Comput. Syst., 2022

HDnn-PIM: Efficient in Memory Design of Hyperdimensional Computing with Feature Extraction.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Efficient and Secure Learning across Memory Hierarchy
PhD thesis, 2021

Stochastic-HD: Leveraging Stochastic Computing on Hyper-Dimensional Computing.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Massively Parallel Big Data Classification on a Programmable Processing In-Memory Architecture.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Invited: Accelerating Fully Homomorphic Encryption with Processing in Memory.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory Architectures.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

PIM-DL: Boosting DNN Inference on Digital Processing In-Memory Architectures via Data Layout Optimizations.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020
SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CryptoPIM: In-memory Acceleration for Lattice-based Cryptographic Hardware.
IACR Cryptol. ePrint Arch., 2020

Trustworthy AI Inference Systems: An Industry Research View.
CoRR, 2020

Multi-label HD Classification in 3D Flash.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Deep Learning Acceleration using Digital-Based Processing In-Memory.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

DUAL: Acceleration of Clustering Algorithms using Digital-based Processing In-Memory.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Implementing binary neural networks in memory with approximate accumulation.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

THRIFTY: Training with Hyperdimensional Computing across Flash Hierarchy.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Deep Learning Acceleration with Neuron-to-Memory Transformation.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

SCRIMP: A General Stochastic Computing Architecture using ReRAM in-Memory Processing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
NVQuery: Efficient Query Processing in Nonvolatile Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

NNPIM: A Processing In-Memory Architecture for Neural Network Acceleration.
IEEE Trans. Computers, 2019

Hardware-Software Co-design to Accelerate Neural Network Applications.
ACM J. Emerg. Technol. Comput. Syst., 2019

Digital-based processing in-memory: a highly-parallel accelerator for data intensive applications.
Proceedings of the International Symposium on Memory Systems, 2019

MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

RAPID: A ReRAM Processing in-Memory Architecture for DNA Sequence Alignment.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

FloatPIM: in-memory acceleration of deep neural network training with high precision.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

UPIM: Unipolar Switching Logic for High Density Processing-in-Memory Applications.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

DigitalPIM: Digital-based Processing In-Memory for Big Data Acceleration.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Exploring Processing In-Memory for Different Technologies.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

HDCluster: An Accurate Clustering Using Brain-Inspired High-Dimensional Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Thermal-Aware Design and Management for Search-based In-Memory Acceleration.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

GRAM: graph processing in a ReRAM-based computational memory.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

FACH: FPGA-based acceleration of hyperdimensional computing by reducing computational complexity.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
RAPIDNN: In-Memory Deep Neural Network Acceleration Framework.
CoRR, 2018

GAS: A Heterogeneous Memory Architecture for Graph Processing.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

RMAC: Runtime Configurable Floating Point Multiplier for Approximate Computing.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

RNSnet: In-Memory Neural Network Acceleration Using Residue Number System.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

FELIX: fast and energy-efficient logic in memory.
Proceedings of the International Conference on Computer-Aided Design, 2018

GenPIM: Generalized processing in-memory to accelerate data intensive applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Efficient query processing in crossbar memory.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Ultra-Efficient Processing In-Memory for Data Intensive Applications.
Proceedings of the 54th Annual Design Automation Conference, 2017


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