Feibin Xiang

According to our database, Feibin Xiang authored at least 4 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design.

Chaojie He, Zi Wang, Feibin Xiang, Zhuoyu Dai, Yifan He, Jinshan Yue, Yongpan Liu

IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

2023

P³ ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer.

Xiangqu Fu, Qirui Ren, Hao Wu, Feibin Xiang, Qing Luo, Jinshan Yue, Yong Chen, Feng Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing.

Zhuoyu Dai, Feibin Xiang, Chaojie He, Zi Wang, Woyu Zhang, Yi Li, Jinshan Yue, Dashan Shang

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture.

Zi Wang, Jinshan Yue, Chaojie He, Zhuoyu Dai, Feibin Xiang, Zhaori Cong, Yifan He, Xiaoyu Feng, Yongpan Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023