Zhuoyu Dai

According to our database, Zhuoyu Dai authored at least 11 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A 28-nm Computing-in-Memory Processor With Zig-Zag Backbone-Systolic CIM and Block-/Self-Gating CAM for NN/Recommendation Applications.

Shengzhe Yan, Zhuoyu Dai, Zhaori Cong, Zeyu Guo, Yifan He, Wenyu Sun, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu, Ming Liu

IEEE J. Solid State Circuits, June, 2026

An area/energy-efficient RRAM computing-in-memory macro with fully-charge-domain multi-bit computation.

Zhi Li, Shengzhe Yan, Jun Wang, Zhuoyu Dai, Zeyu Guo, Zhaori Cong, Zhihang Qian, Xiangqu Fu, Xu Zheng, Chunmeng Dou, Dashan Shang, Jinshan Yue

Sci. China Inf. Sci., 2026

2025

A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications.

Jun Wang, Shengzhe Yan, Xiangqu Fu, Zhihang Qian, Zhi Li, Zeyu Guo, Zhuoyu Dai, Zhaori Cong, Chunmeng Dou, Feng Zhang, Jinshan Yue, Dashan Shang

IEEE Trans. Very Large Scale Integr. Syst., August, 2025

An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet.

Zhihang Qian, Shengzhe Yan, Zhuoyu Dai, Zeyu Guo, Zhaori Cong, Yifan He, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu

IEEE Trans. Very Large Scale Integr. Syst., July, 2025

A monolithic 3D IGZO-RRAM-SRAM-integrated architecture for robust and efficient compute-in-memory enabling equivalent-ideal device metrics.

Shengzhe Yan, Zhaori Cong, Zi Wang, Zhuoyu Dai, Zeyu Guo, Zhihang Qian, Xufan Li, Xu Zheng, Chuanke Chen, Nianduan Lu, Chunmeng Dou, Guanhua Yang, Xiaoxin Xu, Di Geng, Jinshan Yue, Lingfei Wang, Ling Li, Ming Liu

Sci. China Inf. Sci., 2025

2024

A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices.

Zhuoyu Dai, Feibin Xiang, Xiangqu Fu, Yifan He, Wenyu Sun, Yongpan Liu, Guanhua Yang, Feng Zhang, Jinshan Yue, Ling Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design.

Chaojie He, Zi Wang, Feibin Xiang, Zhuoyu Dai, Yifan He, Jinshan Yue, Yongpan Liu

IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications.

Zhuoyu Dai, Shengzhe Yan, Zhaori Cong, Zeyu Guo, Yifan He, Wenyu Sun, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu, Ming Liu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications.

Zeyu Guo, Jinshan Yue, Shengzhe Yan, Zhuoyu Dai, Xiangqu Fu, Zhaori Cong, Zening Niu, Ke Hu, Lihua Xu, Jiawei Wang, Lingfei Wang, Guanhua Yang, Di Geng, Ling Li

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing.

Zhuoyu Dai, Feibin Xiang, Chaojie He, Zi Wang, Woyu Zhang, Yi Li, Jinshan Yue, Dashan Shang

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture.

Zi Wang, Jinshan Yue, Chaojie He, Zhuoyu Dai, Feibin Xiang, Zhaori Cong, Yifan He, Xiaoyu Feng, Yongpan Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023