Xiangqu Fu

According to our database, Xiangqu Fu authored at least 10 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A Multicore Programmable Variable-Precision Near-Memory Accelerator for CNN and Transformer Models.

Yiming Yang, Yiyang Yuan, Xinghua Wang, Xiaoran Li, Hao Wu, Qihao Liu, Weiye Tang, Xiangqu Fu, Feng Zhang

IEEE J. Solid State Circuits, June, 2026

An area/energy-efficient RRAM computing-in-memory macro with fully-charge-domain multi-bit computation.

Zhi Li, Shengzhe Yan, Jun Wang, Zhuoyu Dai, Zeyu Guo, Zhaori Cong, Zhihang Qian, Xiangqu Fu, Xu Zheng, Chunmeng Dou, Dashan Shang, Jinshan Yue

Sci. China Inf. Sci., 2026

2025

A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications.

Jun Wang, Shengzhe Yan, Xiangqu Fu, Zhihang Qian, Zhi Li, Zeyu Guo, Zhuoyu Dai, Zhaori Cong, Chunmeng Dou, Feng Zhang, Jinshan Yue, Dashan Shang

IEEE Trans. Very Large Scale Integr. Syst., August, 2025

SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer.

Xiangqu Fu, Jinshan Yue, Muhammad Faizan, Zhi Li, Qiang Huo, Feng Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025

Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory.

Yi Li, Zijian Ye, Xiangqu Fu, Songqi Wang, Shucheng Du, Ning Lin, Dashan Shang, Jinshan Yue, Zhongrui Wang, Xiaojuan Qi, Feng Zhang, Han Wang

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices.

Zhuoyu Dai, Feibin Xiang, Xiangqu Fu, Yifan He, Wenyu Sun, Yongpan Liu, Guanhua Yang, Feng Zhang, Jinshan Yue, Ling Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity.

Hao Wu, Yong Chen, Yiyang Yuan, Jinshan Yue, Xiangqu Fu, Qirui Ren, Qing Luo, Pui-In Mak, Xinghua Wang, Feng Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications.

Zeyu Guo, Jinshan Yue, Shengzhe Yan, Zhuoyu Dai, Xiangqu Fu, Zhaori Cong, Zening Niu, Ke Hu, Lihua Xu, Jiawei Wang, Lingfei Wang, Guanhua Yang, Di Geng, Ling Li

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

P³ ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer.

Xiangqu Fu, Qirui Ren, Hao Wu, Feibin Xiang, Qing Luo, Jinshan Yue, Yong Chen, Feng Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF.

Qirui Ren, Qiang Huo, Zhisheng Chen, Qi Gao, Yiming Wang, Yiming Yang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei, Xinghua Wang, Feng Zhang, Yong Chen, Pui-In Mak

IEEE Trans. Very Large Scale Integr. Syst., February, 2023