Yifan He
Orcid: 0009-0007-1320-6226Affiliations:
- Tsinghua University, Department of Electronic Engineering, Beijing, China
According to our database1,
Yifan He authored at least 36 papers
between 2020 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2026
A 28-nm Computing-in-Memory Processor With Zig-Zag Backbone-Systolic CIM and Block-/Self-Gating CAM for NN/Recommendation Applications.
IEEE J. Solid State Circuits, June, 2026
An Area-Efficient Lookup-Table -Based eDRAM Digital CIM Macro for Neural Network Inference.
IEEE J. Solid State Circuits, April, 2026
CCE: A Content Creation Engine With Outlier and Mixed-Representation Computing, Semantic-Defined Instruction Generation for Video Diffusion.
IEEE J. Solid State Circuits, March, 2026
2025
An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet.
IEEE Trans. Very Large Scale Integr. Syst., July, 2025
Enabling Energy-Efficient Homomorphic Encryption Evaluation via eDRAM-Based In-Situ Computing in an Edge Processor.
IEEE J. Solid State Circuits, July, 2025
A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference.
IEEE J. Solid State Circuits, February, 2025
CCE: A 28nm Content Creation Engine with Asymmetric Computing, Semantic-Driven Instruction Generation and Collision-Free Outlier Mapper for Video Generation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI Tasks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
A Heterogeneous Microprocessor for Intermittent AI Inference Using Nonvolatile-SRAM-Based Compute-In-Memory.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture.
IEEE J. Solid State Circuits, August, 2024
An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update.
IEEE J. Solid State Circuits, May, 2024
LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024
A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
34.7 A 28nm 2.4Mb/mm<sup>2</sup> 6.9 - 16.3TOPS/mm<sup>2</sup> eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A Unified Microrobotic Visual-Perception Processor with 62.2-FPS/mm<sup>2</sup> and 103-uJ/frame Navigation in 28nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.
IEEE J. Solid State Circuits, 2022
Mixed-Precision Continual Learning Based on Computational Resistance Random Access Memory.
Adv. Intell. Syst., 2022
C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
ACM Trans. Design Autom. Electr. Syst., 2021
A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020