Jishen Zhao

According to our database1, Jishen Zhao authored at least 82 papers between 2010 and 2022.

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Bibliography

2022
Enabling Efficient Large-Scale Deep Learning Training with Cache Coherent Disaggregated Memory Systems.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
Characterizing and Modeling Nonvolatile Memory Systems.
IEEE Micro, 2021

Learning Bounded Context-Free-Grammar via LSTM and the Transformer: Difference and Explanations.
CoRR, 2021

Ayudante: A Deep Reinforcement Learning Approach to Assist Persistent Memory Programming.
Proceedings of the 2021 USENIX Annual Technical Conference, 2021

Suraksha: A Framework to Analyze the Safety Implications of Perception Design Choices in AVs.
Proceedings of the 32nd IEEE International Symposium on Software Reliability Engineering, 2021

FPRA: A Fine-grained Parallel RRAM Architecture.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Learn-to-Share: A Hardware-friendly Transfer Learning Framework Exploiting Computation and Parameter Sharing.
Proceedings of the 38th International Conference on Machine Learning, 2021

ProFlip: Targeted Trojan Attack with Progressive Bit Flips.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

Continuous Cnn For Nonuniform Time Series.
Proceedings of the IEEE International Conference on Acoustics, 2021

Suraksha: A Quantitative AV Safety Evaluation Framework to Analyze Safety Implications of Perception Design Choices.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2021

A Physical-Aware Framework for Memory Network Design Space Exploration.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Enhancing Model Parallelism in Neural Architecture Search for Multidevice System.
IEEE Micro, 2020

Efficient Implementation of Multi-Channel Convolution in Monolithic 3D ReRAM Crossbar.
CoRR, 2020

Characterizing and Modeling Non-Volatile Memory Systems.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Safety Score: A Quantitative Approach to Guiding Safety-Aware Autonomous Vehicle Computing System Design.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2020

Implementing binary neural networks in memory with approximate accumulation.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Deep Symbolic Superoptimization Without Human Knowledge.
Proceedings of the 8th International Conference on Learning Representations, 2020

Driving Scenario Perception-Aware Computing System Design in Autonomous Vehicles.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

An Order Sampling Processing-in-Memory Architecture for Approximate Graph Pattern Mining.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Vehicular and Edge Computing for Emerging Connected and Autonomous Vehicle Applications.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

SubZero: zero-copy IO for persistent main memory file systems.
Proceedings of the APSys '20: 11th ACM SIGOPS Asia-Pacific Workshop on Systems, 2020

2019
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.
IEEE Trans. Parallel Distributed Syst., 2019

GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Emerging Memory Technologies.
IEEE Micro, 2019

A Neural-based Program Decompiler.
CoRR, 2019

Towards Safety-Aware Computing System Design in Autonomous Vehicles.
CoRR, 2019

Basic Performance Measurements of the Intel Optane DC Persistent Memory Module.
CoRR, 2019

Vorpal: Vector Clock Ordering For Large Persistent Memory Systems.
Proceedings of the 2019 ACM Symposium on Principles of Distributed Computing, 2019

Coda: An End-to-End Neural Program Decompiler.
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019

DeepMarks: A Secure Fingerprinting Framework for Digital Rights Management of Deep Learning Models.
Proceedings of the 2019 on International Conference on Multimedia Retrieval, 2019

SSP: Eliminating Redundant Writes in Failure-Atomic NVRAMs via Shadow Sub-Paging.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Binary Star: Coordinated Reliability in Heterogeneous Memory Systems for High Performance and Scalability.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Transitioning scientific applications to using non-volatile memory for resilience.
Proceedings of the International Symposium on Memory Systems, 2019

HR<sup>3</sup>AM: A Heat Resilient Design for RRAM-based Neuromorphic Computing.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

DeepAttest: an end-to-end attestation framework for deep neural networks.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

DeepInspect: A Black-box Trojan Detection and Mitigation Framework for Deep Neural Networks.
Proceedings of the Twenty-Eighth International Joint Conference on Artificial Intelligence, 2019

Persistent Memory Workload Characterization: A Hardware Perspective.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

Rorg: Service Robot Software Management with Linux Containers.
Proceedings of the International Conference on Robotics and Automation, 2019

GenUnlock: An Automated Genetic Algorithm Framework for Unlocking Logic Encryption.
Proceedings of the International Conference on Computer-Aided Design, 2019

String Figure: A Scalable and Elastic Memory Network Architecture.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

SimBNN: A Similarity-Aware Binarized Neural Network Acceleration Framework.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

PMTest: A Fast and Flexible Testing Framework for Persistent Memory Programs.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Processing-in-Memory for Energy-Efficient Neural Network Training: A Heterogeneous Approach.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Leveraging MLC STT-RAM for energy-efficient CNN training.
Proceedings of the International Symposium on Memory Systems, 2018

Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory Systems.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Reducing NVM Writes with Optimized Shadow Paging.
Proceedings of the 10th USENIX Workshop on Hot Topics in Storage and File Systems, 2018

2017
Overview of 3-D Architecture Design Opportunities and Techniques.
IEEE Des. Test, 2017

Logging in persistent memory: to cache, or not to cache?
Proceedings of the International Symposium on Memory Systems, 2017

Approximate image storage with multi-level cell STT-MRAM main memory.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories.
J. Comput. Sci. Technol., 2016

A unified memory network architecture for in-memory computing in commodity servers.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Integrated Thermal Analysis for Processing In Die-Stacking Memory.
Proceedings of the Second International Symposium on Memory Systems, 2016

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Performance Implications of Processing-in-Memory Designs on Data-Intensive Applications.
Proceedings of the 45th International Conference on Parallel Processing Workshops, 2016

Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Die-stacking Architecture
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2015

Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion.
ACM Trans. Archit. Code Optim., 2015

Memory and Storage System Design with Nonvolatile Memory Technologies.
IPSJ Trans. Syst. LSI Des. Methodol., 2015

Leveraging nonvolatility for architecture design with emerging NVM.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

ThyNVM: enabling software-transparent crash consistency in persistent memory systems.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

DimNoC: a dim silicon approach towards power-efficient on-chip network.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Core vs. uncore: the heart of darkness.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013
Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface.
ACM Trans. Archit. Code Optim., 2013

Kiln: closing the performance gap between systems with and without persistence support.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
MAGE: adaptive granularity and ECC for resilient and power efficient memory systems.
Proceedings of the SC Conference on High Performance Computing Networking, 2012

Energy-efficient GPU design with reconfigurable in-package graphics memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
Moguls: a model to explore the memory hierarchy for bandwidth improvements.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Bandwidth-aware reconfigurable cache design with hybrid memory technologies.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

An energy-efficient 3D CMP design with fine-grained voltage scaling.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Cost-aware three-dimensional (3D) many-core multiprocessor design.
Proceedings of the 47th Design Automation Conference, 2010

Architectural benefits and design challenges for three-dimensional integrated circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010


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