Florentin Dartu

According to our database1, Florentin Dartu authored at least 21 papers between 1993 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
To do or not to do hierarchical timing?
Proceedings of the International Symposium on Physical Design, 2013

2010
Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2006
Algorithms for MIS vector generation and pruning.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005
Weibull-based analytical waveform model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Expanding the frequency range of AWE via time shifting.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Variability modeling and variability-aware design in deep submicron integrated circuits.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd Design Automation Conference, 2005

Piece-wise approximations of RLCK circuit responses using moment matching.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Modeling unbuffered latches for timing analysis.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Statistical gate delay model considering multiple input switching.
Proceedings of the 41th Design Automation Conference, 2004

2002
TETA: transistor-level waveform evaluation for timing analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Timed pattern generation for noise-on-delay calculation.
Proceedings of the 39th Design Automation Conference, 2002

1998
TETA: Transistor-Level Engine for Timing Analysis.
Proceedings of the 35th Conference on Design Automation, 1998

1997
CMOS Gate Delay Models for General RLC Loading.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Performance computation for precharacterized CMOS gates with RC loads.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response.
Proceedings of the 33st Conference on Design Automation, 1996

RC-Interconnect Macromodels for Timing Simulation.
Proceedings of the 33st Conference on Design Automation, 1996

1994
RC interconnect synthesis-a moment fitting approach.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A Gate-Delay Model for high-Speed CMOS Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


  Loading...