Gabriela Nicolescu

According to our database1, Gabriela Nicolescu authored at least 113 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
On the benchmarking of partitioned real-time systems.
CoRR, 2020

Simulator-Based Framework towards Improved Cache Predictability for Multi-Core Avionic Systems.
Proceedings of the Spring Simulation Conference, 2020

2019
Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS.
ACM Trans. Embed. Comput. Syst., 2019

2018
Towards Maximum Energy Efficiency in Nanophotonic Interconnects with Thermal-Aware On-Chip Laser Tuning.
IEEE Trans. Emerg. Top. Comput., 2018

ImGA: an improved genetic algorithm for partitioned scheduling on heterogeneous multi-core systems.
Des. Autom. Embed. Syst., 2018

Towards using DEVS for modelling adaptive storytelling in virtual games.
Proceedings of the 50th Computer Simulation Conference, 2018

From Swarms to Stars: Task Coverage in Robot Swarms with Connectivity Constraints.
Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018

DeEPeR: Enhancing Performance and Reliability in Chip-Scale Optical Interconnection Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Silicon Photonic Interconnects: Minimizing the Controller Latency.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
HypAp: A Hypervolume-Based Approach for Refining the Design of Embedded Systems.
IEEE Embed. Syst. Lett., 2017

Scheduling real-time systems with cyclic dependence using data criticality.
Des. Autom. Embed. Syst., 2017

An analysis of random cache effects on real-time multi-core scheduling algorithms.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

Co-design of a low-latency centralized controller for silicon photonic multistage MZI-based switches.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

2016
Tuning framework for stencil computation in heterogeneous parallel platforms.
J. Supercomput., 2016

Design and Modelling of a Low-Latency Centralized Controller for Optical Integrated Networks.
IEEE Commun. Lett., 2016

Modelling and simulation of optical integrated networks for early-stage design exploration (WIP).
Proceedings of the Summer Computer Simulation Conference, 2016

Rollback-based simulation for the design of continuous/discrete simulation tools.
Proceedings of the Summer Computer Simulation Conference, 2016

A simulation-based model generator for software performance estimation.
Proceedings of the Summer Computer Simulation Conference, 2016

Simulation-based schedulability assessment for real-time systems.
Proceedings of the Summer Computer Simulation Conference, 2016

Cluster-based architecture relying on Optical Integrated Networks with the provision of a low-latency arbiter.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Schedulability-guided exploration of multi-core systems.
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

A Systematic Approach for Privilege Escalation Prevention.
Proceedings of the 2016 IEEE International Conference on Software Quality, 2016

Towards a fast centralized controller for integrated silicon photonic multistage MZI-based switches.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

Photonic integrated circuits: A study on process variations.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A generic conceptual framework based on formal representation for the design of continuous/discrete co-simulation tools.
Des. Autom. Embed. Syst., 2015

Thermal aware design method for VCSEL-based on-chip optical interconnect.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Energy-efficient optical crossbars on chip with multi-layer deposited silicon.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Optical crossbars on chip, a comparative study based on worst-case losses.
Concurr. Comput. Pract. Exp., 2014

A reconfigurable optical network on chip for streaming applications.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Fast and accurate implementation of Canny edge detector on embedded many-core platform.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Efficient transient thermal simulation of 3D ICs with liquid-cooling and through silicon vias.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Chameleon: Channel efficient Optical Network-on-Chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Reduction methods for adapting optical network on chip topologies to 3D architectures.
Microprocess. Microsystems, 2013

Potential and pitfalls of silicon photonics computing and interconnect.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Explicit transient thermal simulation of liquid-cooled 3D ICs.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip.
ACM Trans. Embed. Comput. Syst., 2012

MpAssign: a framework for solving the many-core platform mapping problem.
Softw. Pract. Exp., 2012

Automated Generation of Custom Processor Core from C Code.
J. Electr. Comput. Eng., 2012

On the Verification of a WiMax Design Using Symbolic Simulation.
Proceedings of the Proceedings Fourth International Symposium on Symbolic Computation in Software Science, 2012

Parallelization strategies of the canny edge detector for multi-core CPUs and many-core GPUs.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Embedded system verification through constraint-based scheduling.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

2011
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method.
ACM J. Emerg. Technol. Comput. Syst., 2011

Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC).
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Multi-granularity thermal evaluation of 3D MPSoC architectures.
Proceedings of the Design, Automation and Test in Europe, 2011

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology.
Proceedings of the Design, Automation and Test in Europe, 2011

A multi-objective decision-theoretic exploration algorithm for platform-based design.
Proceedings of the Design, Automation and Test in Europe, 2011

A linear-time approach for the transient thermal simulation of liquid-cooled 3d ics.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
Combining mapping and partitioning exploration for NoC-based embedded systems.
J. Syst. Archit., 2010

Multi-Optical Network-on-Chip for Large Scale MPSoC.
IEEE Embed. Syst. Lett., 2010

Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

MpAssign: A framework for solving the many-core platform mapping problem.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Timing verification of cyclic systems based on temporal constraint analysis.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Model-Based Design for Embedded Systems.
Computational Analysis, Synthesis, and Design of Dynamic Systems, CRC Press, ISBN: 978-1-420-06784-2, 2010

2009
Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications.
J. Signal Process. Syst., 2009

Rapid systems prototyping at RSP'06.
Microelectron. J., 2009

Modeling and Formal Verification of a Passive Optical Network on Chip Behavior.
Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2009

Emerging Technologies and Nanoscale Computing Fabrics.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

Hybrid modeling of opto-electrical interfaces using DEVS and modelica.
Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009, 2009

Embedded tutorial - Understanding multicore technologies.
Proceedings of the Design, Automation and Test in Europe, 2009

Co-simulation based platform for wireless protocols design explorations.
Proceedings of the Design, Automation and Test in Europe, 2009

Optimizing Configuration and Application Mapping for MPSoC Architectures.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
Semantics for Model-Based Validation of Continuous/Discrete Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

Reliable performance analysis of a multicore multithreaded system-on-chip.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Semantics for Rollback-Based Continuous/Discrete Simulation.
Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008

2007
Buffer and Register Allocation for Memory Space Optimization.
J. VLSI Signal Process., 2007

MPSoC memory optimization using program transformation.
ACM Trans. Design Autom. Electr. Syst., 2007

Generic discrete-continuous simulation model for accurate validation in heterogeneous systems design.
Microelectron. J., 2007

A formalization of global simulation models for continuous/discrete systems.
Proceedings of the 2007 Summer Computer Simulation Conference, 2007

Towards the High-Level Design of Optical Networks-on-Chip. Formalization of Opto-Electrical Interfaces.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

MPSoC memory optimization for digital camera applications.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

System level assessment of an optical NoC in an MPSoC platform.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Two-level tiling for MPSoC architecture.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A new efficient EDA tool design methodology.
ACM Trans. Embed. Comput. Syst., 2006

Integration of Configurable Processors in a Multiprocessor Platform.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Application-Level Memory Optimization for MPSoC.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Formal Definitions of Simulation Interfaces in a Continuous/Discrete Co-Simulation Tool.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

A Platform for Refinement of OS Services for Embedded Systems.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Soft-error classification and impact analysis on real-time operating systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Survey of Biological High Performance Computing: Algorithms, Implementations and Outlook Research.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

Buffer and register allocation for memory space optimization.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Codis - a Framework for continuous/discrete Systems Co-simulation.
Proceedings of the 2nd IFAC Conference on Analysis and Design of Hybrid Systems, 2006

2005
A Multiprocessor SoC Platform and Tools for Communications Applications.
Proceedings of the Embedded Systems Handbook., 2005

Leveraging Model Representations for System Level Design Tools.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Discrete-Continuous Simulation Model for Accurate Validation in Component-Based Heterogeneous SoC Design.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Component-Based Methodology for Hardware Design of a Dataflow Processing Network.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

MP SoCs Including Optical Interconnect. Technological Progresses and Challenges for CAD Tools Design.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

2004
Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits.
J. Syst. Softw., 2004

ESys.Net: a new solution for embedded systems modeling and simulation.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation.
Proceedings of the 2004 Design, 2004

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Multi-Level Software Validation for NoC.
Proceedings of the Networks on Chip, 2003

2002
Spécification et validation des systèmes hétérogènes embarqués. (Specification and validation for heterogeneous embedded systems).
PhD thesis, 2002

Desiderata pour la spécification et la conception des systèmes électroniques.
Tech. Sci. Informatiques, 2002

Multiprocessor SoC Platforms: A Component-Based Design Approach.
IEEE Des. Test Comput., 2002

Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Validation in a Component-Based Design Flow for Multicore SoCs.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design.
Proceedings of the 2002 Design, 2002

Component-based design approach for multicore SoCs.
Proceedings of the 39th Design Automation Conference, 2002

2001
Colif: A Design Representation for Application-Specific Multiprocessor SOCs.
IEEE Des. Test Comput., 2001

Colif: a Multilevel Design Representation for Application-Specific Multiprocessor System-on-Chip Design.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

A model for describing communication between aggregate objects in the specification and design of embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Mixed-level cosimulation for fine gradual refinement of communication in SoC design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A generic wrapper architecture for multi-processor SoC cosimulation and design.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

A higher level system communication model for object-oriented specification and design of embedded systems.
Proceedings of ASP-DAC 2001, 2001

Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures.
Proceedings of ASP-DAC 2001, 2001

2000
Interlanguage Communication Synthesis for Heterogeneous Specifications.
Des. Autom. Embed. Syst., 2000

Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Towards design and validation of mixed-technology SOCs.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000


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