Frank Poehl

According to our database1, Frank Poehl authored at least 8 papers between 1999 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2012
Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2010
Production test challenges for highly integrated mobile phone SOCs - A case study.
Proceedings of the 15th European Test Symposium, 2010

2007
On-chip evaluation, compensation and storage of scan diagnosis data.
IET Comput. Digit. Tech., 2007

2006
On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture.
Proceedings of the 11th European Test Symposium, 2006

2005
Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.
Proceedings of the 2005 Design, 2005

2003
Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

1999
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements.
J. Electron. Test., 1999


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