Frédéric Gaffiot

IEEE Trans. Very Large Scale Integr. Syst., 2007

CNTFET Modeling and Reconfigurable Logic-Circuit Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A Family of Ultra-Fine Grain CNTFET-based Reconfigurable Logic Gates.

[BibT_eX]

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Design of a Novel CNTFET-based Reconfigurable Logic Gate.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A 100Hz 5nT/Hz Low-Pass ΔΣ Servo-Controlled Microfluxgate Magnetometer Using Pulsed Excitation.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Ultra-fine grain reconfigurability using CNTFETs.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

System level assessment of an optical NoC in an MPSoC platform.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Novel CNTFET-based Reconfigurable Logic Gate Design.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

A Sigma-Delta closed-loop digital microfluxgate magnetometer.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

Heterogeneous Modelling of an Optical Network-on-Chip with SystemC.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Towards reconfigurable optical networks on chip.

[BibT_eX]

Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

UML/XML based approach to hierarchical AMS Synthesis.

[BibT_eX]

[DOI]

G. Revy

Proceedings of the Forum on specification and Design Languages, 2005

VHDL & VHDL-AMS Modelling and Simulation of a CMOS Imager IP.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2005

2004

Simulation of Electrical and Optical Interconnections for Future VLSI ICs.

[BibT_eX]

[DOI]

Proceedings of the Computational Science, 2004

RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-Ends.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Design and Behavioral Modeling Tools for Optical Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

On-Chip Optical Interconnect for Low-Power.

[BibT_eX]

[DOI]

Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003

Design Methodologies for High-Speed CMOS Photoreceiver Front-Ends.

[BibT_eX]

[DOI]

Fabien Mieyeville

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

Predictive design space exploration of maximum bandwidth CMOS photoreceiver preamplifiers.

[BibT_eX]

[DOI]

Fabien Mieyeville

Grzegorz Tosik

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Hierarchical synthesis of high-speed CMOS photoreceiver front-ends using a multi-domain behavioural description language.

[BibT_eX]

[DOI]

Fabien Mieyeville

Proceedings of the Forum on specification and Design Languages, 2003

A VHDL-AMS library of hierarchical optoelectronic device models.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2003

2000

Design and Optimization of Optical Links Based on VHDL-AMS Modeling.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000

1998

FLAG: a flexible layout generator for analog MOS transistors.

[BibT_eX]

[DOI]

Hervé Mathias

Josette Berger-Toussan

Gilles Jacquemod