Ganapathy Parthasarathy

According to our database, Ganapathy Parthasarathy authored at least 21 papers between 1998 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Optimizing Constrained Random Verification with ML and Bayesian Estimation.

Bhuvnesh Kumar, Ganapathy Parthasarathy, Saurav Nanda, Sridhar Rajakumar

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

2022

Optimizing ML Classification Models for Constrained EDA Resource Budgets.

Ganapathy Parthasarathy, Bhuvnesh Kumar, Saurav Nanda, Parivesh Choudhary, Sridhar Rajakumar

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

RTL Regression Test Selection using Machine Learning.

Ganapathy Parthasarathy, Aabid Rushdi, Parivesh Choudhary, Saurav Nanda, Malan Evans, Hansika Gunasekara, Sridhar Rajakumar

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2019

Resource Aware Scheduling for EDA Regression Jobs.

Saurav Nanda, Ganapathy Parthasarathy, Parivesh Choudhary, Arun Venkatachar

Proceedings of the Euro-Par 2019: Parallel Processing Workshops, 2019

2017

Test Knowledge Data Base.

Arun Venkatachar, S. Rajakumar, M. Chapman, Sajeewan Basuru, Ganapathy Parthasarathy, C.-C. Lin, A. Hegde, T. Li

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2005

RTL SAT simplification by Boolean and interval arithmetic reasoning.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

An Efficient Sequential SAT Solver With Improved Search Strategies.

Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen

Proceedings of the 2005 Design, 2005

Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver.

Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng

Proceedings of the 2005 Design, 2005

Structural search for RTL with predicate learning.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer

Proceedings of the 42nd Design Automation Conference, 2005

2004

Safety Property Verification Using Sequential SAT and Bounded Model Checking.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang

IEEE Des. Test Comput., 2004

An efficient finite-domain constraint solver for circuits.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang

Proceedings of the 41th Design Automation Conference, 2004

Efficient reachability checking using sequential SAT.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

SATORI - A Fast Sequential SAT Engine for Circuits.

Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A comparison of BDDs, BMC, and sequential SAT for model checking.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

2002

Efficient circuit clustering for area and power reduction in FPGAs.

Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska

ACM Trans. Design Autom. Electr. Syst., 2002

Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.

Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Interconnect complexity-aware FPGA placement using Rent's rule.

Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Interconnect Resource-Aware Placement for Hierarchical FPGAs.

Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

An analysis of ATPG and SAT algorithms for formal verification.

Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

1999

Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method.

Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion.

Ganapathy Parthasarathy, Michael L. Bushnell

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998