Huaguo Liang

According to our database, Huaguo Liang authored at least 113 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Self-Biased Current Reference Source-Based Pre-Bond TSV Test Solution.

Jun Liu, Songren Cheng, Tian Chen, Xi Wu, Huaguo Liang

IEEE Trans. Very Large Scale Integr. Syst., April, 2024

Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy.

Zhengfeng Huang, Yan Zhang, Lei Ai, Huaguo Liang, Tianming Ni, Tai Song, Aibin Yan

J. Circuits Syst. Comput., March, 2024

Reliability analysis and comparison of ring-PUF based on probabilistic models.

Jingchang Bian, Zhengfeng Huang, Yankun Lin, Zhao Yang, Huaguo Liang, Tianming Ni

Microelectron. J., February, 2024

A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations.

Jingchang Bian, Zhengfeng Huang, Peng Ye, Zhao Yang, Huaguo Liang

ACM Trans. Design Autom. Electr. Syst., January, 2024

Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement.

Zhengfeng Huang, Jingchang Bian, Yankun Lin, Huaguo Liang, Tianming Ni

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

2023

RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel.

Dongyu Xu, Yiming Ouyang, Wu Zhou, Zhengfeng Huang, Huaguo Liang, Xiaoqing Wen

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator.

Yingchun Lu, Yun Yang, Rong Hu, Huaguo Liang, Maoxiang Yi, Zhengfeng Huang, Yuanming Ma, Tian Chen, Liang Yao

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix.

Zhengfeng Huang, Dongxing Ma, Runwu Ji, Huaguo Liang, Aibin Yan, Tai Song, Tianming Ni

IEEE Trans. Aerosp. Electron. Syst., December, 2023

Improving power and performance of on-chip network through virtual channel sharing and power gating.

Dongyu Xu, Yiming Ouyang, Wu Zhou, Huaguo Liang

Integr., November, 2023

Low-overhead TRNG based on MUX for cryptographic protection using multiphase sampling.

Liang Yao, Huaguo Liang, Yingchun Lu

J. Supercomput., October, 2023

URMP: using reconfigurable multicast path for NoC-based deep neural network accelerators.

Yiming Ouyang, Jiaxin Wang, Chenglong Sun, Qi Wang, Huaguo Liang

J. Supercomput., September, 2023

Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit Degradation Prediction.

Hui Xu, Rui Zhu, Xia Sun, Xianjin Fang, Pan Qi, Huaguo Liang, Zhengfeng Huang

J. Circuits Syst. Comput., August, 2023

Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets.

Zhengfeng Huang, Hao Wang, Dongxing Ma, Huaguo Liang, Yiming Ouyang, Aibin Yan

J. Electron. Test., June, 2023

Design of approximate Booth multipliers based on error compensation.

Yongxia Sheng, Huaguo Liang, Bao Fang, Cuiyun Jiang, Zhengfeng Huang, Maoxiang Yi, Yingchun Lu

Integr., May, 2023

Dynamic detection of wireless interface faults and fault-tolerant routing algorithm in WiNoC.

Yiming Ouyang, Dongyu Xu, Chang Qian, Wu Zhou, Qi Wang, Huaguo Liang

Integr., May, 2023

Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion.

Wu Zhou, Yiming Ouyang, Dongyu Xu, Zhengfeng Huang, Huaguo Liang, Xiaoqing Wen

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

A dynamically reconfigurable entropy source circuit for high-throughput true random number generator.

Liyu Jin, Maoxiang Yi, Yuan Xiao, Lifa Sun, Yingchun Lu, Huaguo Liang

Microelectron. J., March, 2023

Improvement of cell internal weak defects detection under process variation by optimizing test path and test pattern.

Hong Zhang, Huaguo Liang, Jiewen Hu, Zhiwei Shao, Maoxiang Yi, Yingchun Lu, Zhengfeng Huang

Microelectron. J., 2023

Fault-avoidance C-element based low overhead and TNU-resilient latch.

Zhengfeng Huang, Zhouyu Gong, Dongxing Ma, Xiaolei Wang, Yingchun Lu, Wenfa Zhan, Huaguo Liang, Tianming Ni

Microelectron. J., 2023

LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy.

Hui Xu, Jing Zhou, Ruijun Ma, Huaguo Liang, Zhengfeng Huang, Chaoming Liu

Integr., 2023

2022

A router architecture with dual input and dual output channels for Networks-on-Chip.

Wu Zhou, Yiming Ouyang, Yingchun Lu, Huaguo Liang

Microprocess. Microsystems, April, 2022

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator.

Jianguo Cui, Maoxiang Yi, Di Cao, Liang Yao, Xinyu Wang, Huaguo Liang, Zhengfeng Huang, Haochen Qi, Tianming Ni, Yingchun Lu

IEEE Trans. Circuits Syst. II Express Briefs, 2022

M-RO PUF: A portable pure digital RO PUF based on MUX unit.

Liang Yao, Huaguo Liang, Qian Han, Hong Zhang, Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi, Yingchun Lu

Microelectron. J., 2022

A reconfigurable PUF structure with dual working modes based on entropy separation model.

Yanjie Wang, Huaguo Liang, Yuchuan Wang, Liang Yao, Maoxiang Yi, Zhengfeng Huang, Yingchun Lu

Microelectron. J., 2022

REE: Reconfigurable and energy-efficient router architecture in wireless network-on-chip.

Yiming Ouyang, Dongyu Xu, Zhimou Chen, Rongjing Chen, Wu Zhou, Huaguo Liang

Microelectron. J., 2022

Design of fully adaptive routing and hybrid VC allocation in wireless NOC.

Yiming Ouyang, Ruifeng Li, Chunlei Hu, Qi Wang, Yingchun Lu, Huaguo Liang

Microelectron. J., 2022

Architecting a congestion pre-avoidance and load-balanced wireless network-on-chip.

Chenglong Sun, Yiming Ouyang, Huaguo Liang

J. Parallel Distributed Comput., 2022

Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements.

Zhengfeng Huang, Wanshu Zhong, Lanxi Duan, Yue Zhang, Huaguo Liang, Jianan Wang, Tai Song, Yingchun Lu

J. Circuits Syst. Comput., 2022

A reconfigurable test method based on LFSR for 3D stacking integrated circuits.

Chen Tian, Jianyong Lu, Liu Jun, Huaguo Liang, Yingchun Lu, Maoxiang Yi

Integr., 2022

A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design.

Yingchun Lu, Guangzhen Hu, Jianan Wang, Hao Wang, Liang Yao, Huaguo Liang, Maoxiang Yi, Zhengfeng Huang

J. Electron. Test., 2022

A Lightweight M_TRNG Design based on MUX Cell Entropy using Multiphase Sampling.

Liang Yao, Huaguo Liang, Hong Zhang, Tianming Ni, Maoxiang Yi, Yingchun Lu

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System.

Dawen Xu, Ziyang Zhu, Cheng Liu, Ying Wang, Shuang Zhao, Lei Zhang, Huaguo Liang, Huawei Li, Kwang-Ting Cheng

IEEE Trans. Very Large Scale Integr. Syst., 2021

Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator.

Yingchun Lu, Xinyu Wang, Yanjie Wang, Yuan Zhang, Liang Yao, Maoxiang Yi, Zhengfeng Huang, Huaguo Liang

IEEE Trans. Very Large Scale Integr. Syst., 2021

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure.

Xinyu Wang, Huaguo Liang, Yanjie Wang, Liang Yao, Yang Guo, Maoxiang Yi, Zhengfeng Huang, Haochen Qi, Yingchun Lu

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC.

Tianming Ni, Qi Xu, Zhengfeng Huang, Huaguo Liang, Aibin Yan, Xiaoqing Wen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A high reliability physically unclonable function based on multiple tunable ring oscillator.

Yuan Zhang, Huaguo Liang, Liang Yao, Maoxiang Yi, Zhengfeng Huang, Yingchun Lu

Microelectron. J., 2021

Architecting a priority-based dynamic media access control mechanism in Wireless Network-on-Chip.

Yiming Ouyang, Chenglong Sun, Boyuan Jia, Qi Wang, Huaguo Liang

Microelectron. J., 2021

A high-speed and triple-node-upset recovery latch with heterogeneous interconnection.

Zhengfeng Huang, Hao Wang, Yang Ang, Huaguo Liang, Yiming Ouyang, Tianming Ni

Microelectron. J., 2021

LC-TSL: A low-cost triple-node-upset self-recovery latch design based on heterogeneous elements for 22 nm CMOS.

Zhengfeng Huang, Shangjie Pan, Hao Wang, Huaguo Liang, Tianming Ni

Microelectron. J., 2021

Design of MNU-Resilient latches based on input-split C-elements.

Zhengfeng Huang, Xiandong Li, Zhouyu Gong, Huaguo Liang, Yingchun Lu, Yiming Ouyang, Tianming Ni

Microelectron. J., 2021

Design of node separated triple-node-upset self-recoverable latch.

Zhengfeng Huang, Di Cao, Jianguo Cui, Yingchun Lu, Huaguo Liang, Yiming Ouyang, Tianming Ni, Zhenmin Li

Microelectron. J., 2021

Approximate multipliers based on a novel unbiased approximate 4-2 compressor.

Bao Fang, Huaguo Liang, Dawen Xu, Maoxiang Yi, Yongxia Sheng, Cuiyun Jiang, Zhengfeng Huang, Yingchun Lu

Integr., 2021

Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs.

Tai Song, Huaguo Liang, Zhengfeng Huang, Tianming Ni, Ying Sun

IEICE Electron. Express, 2021

Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems.

Qi Wang, Yiming Ouyang, Yingchun Lu, Huaguo Liang, Dakai Zhu

J. Electron. Test., 2021

Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch.

Hui Xu, Cong Sun, Le Zhou, Huaguo Liang, Zhengfeng Huang

IEEE Access, 2021

A N: 1 Single-Channel TDMA Fault-Tolerant Technique for TSVs in 3D-ICs.

Huaguo Liang, Danqing Li, Zhao Yang, Tianming Ni, Zhengfeng Huang, Cuiyun Jiang

Proceedings of the IEEE International Test Conference in Asia, 2021

2020

Architecture of Cobweb-Based Redundant TSV for Clustered Faults.

Tianming Ni, Dongsheng Liu, Qi Xu, Zhengfeng Huang, Huaguo Liang, Aibin Yan

IEEE Trans. Very Large Scale Integr. Syst., 2020

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC.

Tianming Ni, Hao Chang, Tai Song, Qi Xu, Zhengfeng Huang, Huaguo Liang, Aibin Yan, Xiaoqing Wen

IEEE Trans. Circuits Syst., 2020

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults.

Tianming Ni, Yao Yao, Hao Chang, Lin Lu, Huaguo Liang, Aibin Yan, Zhengfeng Huang, Xiaoqing Wen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Design of a Wireless Router with Virtual Channel Fault Tolerant in WiNoC.

Yiming Ouyang, Wu Zhou, Sheng Li, Zhilu Wang, Huaguo Liang, Gaoming Du

J. Circuits Syst. Comput., 2020

cm³WiNoCs: Congestion-Aware Millimeter-Wave Multichannel Wireless Networks-on-Chip.

Dedong Zhao, Yiming Ouyang, Qi Wang, Huaguo Liang

IEEE Access, 2020

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm.

Tai Song, Huaguo Liang, Tianming Ni, Zhengfeng Huang, Yingchun Lu, Jinlei Wan, Aibin Yan

IEEE Access, 2020

A Novel Low-Latency Regional Fault-Aware Fault-Tolerant Routing Algorithm for Wireless NoC.

Yiming Ouyang, Qi Wang, Mengxuan Ru, Huaguo Liang, Jianhua Li

IEEE Access, 2020

Jitter-Quantizing-Based TRNG Robust Against PVT Variations.

Yingchun Lu, Huaguo Liang, Liang Yao, Xinyu Wang, Haochen Qi, Maoxiang Yi, Cuiyun Jiang, Zhengfeng Huang

IEEE Access, 2020

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications.

Aibin Yan, Zhelong Xu, Jie Cui, Zuobin Ying, Zhengfeng Huang, Huaguo Liang, Patrick Girard, Xiaoqing Wen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators.

Dawen Xu, Cheng Chu, Qianlong Wang, Cheng Liu, Ying Wang, Lei Zhang, Huaguo Liang, Kwang-Ting Cheng

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Multi-task Scheduling for PIM-based Heterogeneous Computing System.

Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Xianzhong Zhou, Lei Zhang, Huaguo Liang, Huawei Li

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs.

Maoxiang Yi, Jingchang Bian, Tianming Ni, Cuiyun Jiang, Hao Chang, Huaguo Liang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Design of Wireless Network on Chip with Priority-Based MAC.

Yiming Ouyang, Yang Zhao, Kun Xing, Zhengfeng Huang, Huaguo Liang, Jianhua Li

J. Circuits Syst. Comput., 2019

CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness.

Yiming Ouyang, Zhe Li, Jianhua Li, Chenglong Sun, Huaguo Liang, Gaoming Du

Integr., 2019

DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip.

Yiming Ouyang, Qi Wang, Lizhu Hu, Huaguo Liang

J. Electron. Test., 2019

Temperature-Aware Floorplanning for Fixed-Outline 3D ICs.

Tianming Ni, Hao Chang, Shidong Zhu, Lin Lu, Xueyun Li, Qi Xu, Huaguo Liang, Zhengfeng Huang

IEEE Access, 2019

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory.

Tai Song, Huaguo Liang, Ying Sun, Zhengfeng Huang, Maoxiang Yi, Xiangsheng Fang, Aibin Yan

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells.

Zhiyuan Song, Aibin Yan, Jie Cui, Zhili Chen, Xuejun Li, Xiaoqing Wen, Chaoping Lai, Zhengfeng Huang, Huaguo Liang

Proceedings of the IEEE International Test Conference in Asia, 2019

2018

Design of Low-Power WiNoC with Congestion-Aware Wireless Node.

Yiming Ouyang, Zhe Li, Kun Xing, Zhengfeng Huang, Huaguo Liang, Jianhua Li

J. Circuits Syst. Comput., 2018

An improved communication scheme for non-HOL-blocking wireless NoC.

Yiming Ouyang, Jianfeng Yang, Kun Xing, Zhengfeng Huang, Huaguo Liang

Integr., 2018

MTTF-Aware Reliability Task Scheduling for PIM-Based Heterogeneous Computing System.

Desong Pang, Dawen Xu, Ying Wang, Huaguo Liang

Proceedings of the IEEE International Test Conference in Asia, 2018

Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS.

Qian He, Aibin Yan, Chaoping Lai, Yinlei Zhang, Chunming Liu, Zhile Chen, Zhen Wu, Jie Cui, Huaguo Liang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A High Reliability FPGA Chip Identification Generator Based on PDLs.

Kai Zhou, Huaguo Liang, Yue Jiang, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yao Yao

Proceedings of the 27th IEEE Asian Test Symposium, 2018

An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.

Xiumin Xu, Huaguo Liang, Kai Zhou, Gaoliang Ma, Zhengfeng Huang, Maoxiang Yi, Tianming Ni, Yingchun Lu

Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Low-Cost High-Efficiency True Random Number Generator on FPGAs.

Gaoliang Ma, Huaguo Liang, Liang Yao, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Kai Zhou

Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE.

Zhengfeng Huang, Yangyang Zhang, Zian Su, Huaguo Liang, Huijie Yao, Tianming Ni

Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Dictionary-Based Test Data Compression Method Using Tri-State Coding.

Tian Chen, Chenxin Lin, Huaguo Liang, Fuji Ren

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.

Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yiming Ouyang, Huaguo Liang

IEEE Trans. Very Large Scale Integr. Syst., 2017

A TSV Fault-Tolerant Scheme Based on Failure Classification in 3D-NoC.

Yiming Ouyang, Jian Da, Xiumin Wang, Qianqian Han, Huaguo Liang, Gaoming Du

J. Circuits Syst. Comput., 2017

A Region-Based Through-Silicon via Repair Method for Clustered Faults.

Tianming Ni, Huaguo Liang, Mu Nie, Xiumin Xu, Aibin Yan, Zhengfeng Huang

IEICE Trans. Electron., 2017

Highly Robust Double Node Upset Resilient Hardened Latch Design.

Huaguo Liang, Xin Li, Zhengfeng Huang, Aibin Yan, Xiumin Xu

IEICE Trans. Electron., 2017

A transient pulse dually filterable and online self-recoverable latch.

Aibin Yan, Huaguo Liang, Yingchun Lu, Zhengfeng Huang

IEICE Electron. Express, 2017

A highly reliable butterfly PUF in SRAM-based FPGAs.

Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xiangsheng Fang, Tianming Ni, Maoxiang Yi

IEICE Electron. Express, 2017

A single event transient detector in SRAM-based FPGAs.

Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yingchun Lu, Aibin Yan, Tianming Ni, Maoxiang Yi

IEICE Electron. Express, 2017

Vernier ring based pre-bond through silicon vias test in 3D ICs.

Tianming Ni, Mu Nie, Huaguo Liang, Jingchang Bian, Xiumin Xu, Xiangsheng Fang, Zhengfeng Huang, Xiaoqing Wen

IEICE Electron. Express, 2017

HLDTL: High-performance, low-cost, and double node upset tolerant latch design.

Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Jie Cui, Huaguo Liang

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations.

Aibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xuejun Li

Microelectron. Reliab., 2016

AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip.

Yiming Ouyang, Qi Chen, Xiumin Wang, Xiaoye Ouyang, Huaguo Liang, Gaoming Du

J. Circuits Syst. Comput., 2016

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures.

Tian Chen, Dandan Shen, Xin Yi, Huaguo Liang, Xiaoqing Wen, Wei Wang

IEICE Trans. Inf. Syst., 2016

Co-mitigating circuit PBTI and HCI aging considering NMOS transistor stacking effect.

Maoxiang Yi, Yingxian Gan, Zhengfeng Huang, Huaguo Liang

Proceedings of the International Symposium on Integrated Circuits, 2016

NBTI mitigation by M-IVC with input duty cycle and randomness constraints.

Maoxiang Yi, Xiaohong Liu, Qingwu Wu, Tianming Ni, Zhengfeng Huang, Huaguo Liang

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology.

Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Xiaolin Xu, Huaguo Liang

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology.

Aibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi

IEICE Trans. Electron., 2015

A High Performance SEU Tolerant Latch.

Zhengfeng Huang, Huaguo Liang, Sybille Hellebrand

J. Electron. Test., 2015

Pulse shrinkage based pre-bond through silicon vias test in 3D IC.

Chang Hao, Huaguo Liang

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

NBTI-induced circuit aging optimization by protectability-aware gate replacement technique.

Guimao Zhang, Maoxiang Yi, Yong Miao, Dawen Xu, Huaguo Liang

Proceedings of the 16th Latin-American Test Symposium, 2015

MTTF-Aware Reliability Task Scheduling for Heterogeneous Multicore System.

Huaguo Liang, Yangyang Dai, Maoxiang Yi, Dawen Xu, Zhengfeng Huang

Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2014

Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding.

Chang Hao, Huaguo Liang, Li Yang, Yiming Ouyang

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Design of a Radiation Hardened Latch for Low-Power Circuits.

Huaguo Liang, Zhi Wang, Zhengfeng Huang, Aibin Yan

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

A dynamic self-adaptive correction method for error resilient application.

Luming Yan, Huaguo Liang, Zhengfeng Huang

Proceedings of the Design, Automation and Test in Europe, 2013

2010

A Novel x -ploiting Strategy for Improving Performance of Test Data Compression.

Maoxiang Yi, Huaguo Liang, Lei Zhang, Wenfa Zhan

IEEE Trans. Very Large Scale Integr. Syst., 2010

A scheme of test data compression based on coding of even bits marking and selective output inversion.

Wenfa Zhan, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Aiman H. El-Maleh

Comput. Electr. Eng., 2010

2009

Impact of Hazards on Pattern Selection for Small Delay Defects.

Jie Wang, Huawei Li, Yinghua Min, Xiaowei Li, Huaguo Liang

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding.

Huaguo Liang, Wenfa Zhan, Qiang Luo, Cuiyun Jiang

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Optimal LFSR-Coding Test Data Compression Based on Test Cube Dividing.

Maoxiang Yi, Huaguo Liang, Kaihua Zhan, Cuiyun Jiang

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2008

Balancing wrapper chains of SoC core based on best interchange decreasing.

Maoxiang Yi, Huaguo Liang, Zhengfeng Huang

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies.

Zhengfeng Huang, Huaguo Liang

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A Scheme of Test Pattern Generation Based on Reseeding of Segment-Fixing Counter.

Tian Chen, Huaguo Liang, Minsheng Zhang, Wei Wang

Proceedings of the 9th International Conference for Young Computer Scientists, 2008

2007

Test data compression scheme based on variable-to-fixed-plus-variable-length coding.

Wenfa Zhan, Huaguo Liang, Feng Shi, Zhengfeng Huang

J. Syst. Archit., 2007

A Novel Collaborative Scheme of Test Data Compression Based on Fixed-Plus-variable-Length Coding.

Wenfa Zhan, Huaguo Liang, Feng Shi, Zhengfeng Huang

Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

Block Marking and Updating Coding in Test Data Compression for SoC.

Lei Zhang, Huaguo Liang, Wenfa Zhan, Cuiyun Jiang

Proceedings of the 16th Asian Test Symposium, 2007

2005

A BIST Scheme Based on Selecting State Generation of Folding Counters.

Huaguo Liang, Maoxiang Yi, Xiangsheng Fang, Cuiyun Jiang

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2003

A new technique for deterministic scan based built in self test (BIST).

Huaguo Liang

PhD thesis, 2003

Sharing BIST with Multiple Cores for System-on-a-Chip.

Huaguo Liang, Cuiyun Jiang

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

A Mixed-Mode BIST Scheme Based on Folding Compression.

Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich

J. Comput. Sci. Technol., 2002

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.

Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich

J. Electron. Test., 2002

2001

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.

Sybille Hellebrand, Huaguo Liang, Hans-Joachim Wunderlich

J. Electron. Test., 2001