Xueqian Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Reliability Evaluation of Tidal Current Farm Integrated Generation Systems Considering Wake Effects.

[BibT_eX]

[DOI]

IEEE Access, 2018

2017

A Tool for xMAS-Based Modeling and Analysis of Communication Fabrics in Simulink.

[BibT_eX]

[DOI]

ACM Trans. Model. Comput. Simul., 2017

2015

Network on Chip : Performance Bound and Tightness.

[BibT_eX]

[DOI]

PhD thesis, 2015

Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-Layout RF Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Backlog Bound Analysis for Virtual-Channel Routers.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

An efficient spectral graph sparsification approach to scalable reduction of large flip-chip power grids.

[BibT_eX]

[DOI]

Cheng Zhuo

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Empowering study of delay bound tightness with simulated annealing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Methods for fault tolerance in networks-on-chip.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2013

Per-flow delay bound analysis based on a formalized microarchitectural model.

[BibT_eX]

[DOI]

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

An efficient graph sparsification approach to scalable harmonic balance (HB) analysis of strongly nonlinear RF circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

GPSCP: A general-purpose support-circuit preconditioning approach to large-scale SPICE-accurate nonlinear circuit simulations.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly support-circuit preconditioners.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap Budgeting.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Robust Parallel Preconditioned Power Grid Simulation on GPU With Adaptive Runtime Performance Modeling and Optimization.

[BibT_eX]

[DOI]

Zhiyu Zeng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Power grid analysis with hierarchical support graphs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Fast multipole method on GPU: tackling 3-D capacitance extraction on massively parallel SIMD platforms.

[BibT_eX]

[DOI]