Gaurang Upasani

According to our database, Gaurang Upasani authored at least 9 papers between 2009 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Fifty Years of the International Symposium on Computer Architecture: A Data-Driven Retrospective.

Matthew D. Sinclair, Parthasarathy Ranganathan, Gaurang Upasani, Adrian Sampson, David A. Patterson, Rutwik Jain, Nidhi Parthasarathy, Shaan Shah

IEEE Micro, 2023

Fifty Years of ISCA: A data-driven retrospective on key trends.

Gaurang Upasani, Matthew D. Sinclair, Adrian Sampson, Parthasarathy Ranganathan, David A. Patterson, Shaan Shah, Nidhi Parthasarathy, Rutwik Jain

CoRR, 2023

2016

Soft error mitigation techniques for future chip multiprocessors.

Gaurang Upasani

PhD thesis, 2016

A Case for Acoustic Wave Detectors for Soft-Errors.

Gaurang Upasani, Xavier Vera, Antonio González

IEEE Trans. Computers, 2016

2014

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery.

Gaurang Upasani, Xavier Vera, Antonio González

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Framework for economical error recovery in embedded cores.

Gaurang Upasani, Xavier Vera, Antonio González

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013

Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery.

Gaurang Upasani, Xavier Vera, Antonio González

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012

Setting an error detection infrastructure with low cost acoustic wave detectors.

Gaurang Upasani, Xavier Vera, Antonio González

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2009

Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering.

Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009