Kimon Karras

According to our database1, Kimon Karras authored at least 17 papers between 2008 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
A Hardware Acceleration Platform for AI-Based Inference at the Edge.
Circuits Syst. Signal Process., 2020

2017
EXEGESIS: Extreme Edge Resource Harvesting for a Virtualized Fog Environment.
IEEE Commun. Mag., 2017

Computing, Caching, and Communication at the Edge: The Cornerstone for Building a Versatile 5G Ecosystem.
IEEE Commun. Mag., 2017

Design Space Exploration of LDPC Decoders Using High-Level Synthesis.
IEEE Access, 2017

2015
Scaling Out to a Single-Node 80Gbps Memcached Server with 40Terabytes of Memory.
Proceedings of the 7th USENIX Workshop on Hot Topics in Storage and File Systems, 2015

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
High-Level Synthesis Case Study: Implementation of a Memcached Server.
CoRR, 2014

2013
A network processor architecture for high speed carrier grade ethernet networks.
PhD thesis, 2013

Achieving 10Gbps Line-rate Key-value Stores with FPGAs.
Proceedings of the 5th USENIX Workshop on Hot Topics in Cloud Computing, 2013

2011
Advanced Packet Segmentation and Buffering Algorithms in Network Processors.
Trans. High Perform. Embed. Archit. Compil., 2011

2010
A folded pipeline network processor architecture for 100 Gbit/s networks.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

2008
Improving memory subsystem performance in network processors with smart packet segmentation.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture.
Proceedings of the FPL 2008, 2008

Aeronautical Mobile Ad Hoc Networks.
Proceedings of the European Wireless 2008, 2008

Buffer allocation for advanced packet segmentation in Network Processors.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008


  Loading...