Emmanouil Kalligeros

According to our database1, Emmanouil Kalligeros authored at least 31 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Oracle-based Logic Locking Attacks: Protect the Oracle Not Only the Netlist.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Optimization and Hardware Implementation of Image and Video Watermarking for Low-Cost Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Towards Standardization of MQTT-Alert-based Sensor Networks: Protocol Structures Formalization and Low-End Node Security.
Proceedings of the 13th IEEE International Symposium on Industrial Embedded Systems, 2018

2017
Weighted logic locking: A new approach for IC piracy protection.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Optimization and hardware implementation of image watermarking for low cost applications.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2014
ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

2013
Merged Switch Allocation and Traversal in Network-on-Chip Switches.
IEEE Trans. Computers, 2013

Switch folding: network-on-chip routers with time-multiplexed output ports.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Defect Coverage-Driven Window-Based Test Compression.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
LFSR-based test-data compression with self-stoppable seeds.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Optimal Selective Huffman Coding for Test-Data Compression.
IEEE Trans. Computers, 2007

2006
Efficient Multiphase Test Set Embedding for Scan-based Testing.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Efficient test-data compression for IP cores using multilevel Huffman coding.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Reseeding-Based Test Set Embedding with Reduced Test Sequences.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Power aware test-data compression for scan-based testing.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
Multiphase BIST: a new reseeding technique for high test-data compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
A highly regular multi-phase reseeding technique for scan-based BIST.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation.
J. Syst. Archit., 2002

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST.
J. Electron. Test., 2002

An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

A ROMless LFSR Reseeding Scheme for Scan-based BIST.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
A New Reseeding Technique for LFSR-Based Test Pattern Generation.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

2000
Low Power BIST for Wallace Tree-Based Fast Multipliers.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000


  Loading...