Ghaith Tarawneh

Orcid: 0000-0001-6415-1658

According to our database1, Ghaith Tarawneh authored at least 19 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture.
IET Comput. Digit. Tech., 2022

2018
Significance-Driven Logic Compression for Energy-Efficient Multiplier Design.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Collaborative Content Creation: Impact of Media Type on Author Behavior.
Proceedings of the Companion of the 2018 ACM Conference on Computer Supported Cooperative Work and Social Computing, 2018

Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools.
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017
Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Approximate adder segmentation technique and significance-driven error correction.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Distributed Event-Based Computing.
Proceedings of the Parallel Computing is Everywhere, 2017

Programming Model to Develop Supercomputer Combinatorial Solvers.
Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017

Language and Hardware Acceleration Backend for Graph Processing.
Proceedings of the Languages, Design Methods, and Tools for Electronic System Design, 2017

Energy-efficient approximate multiplier design using bit significance-driven logic compression.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Metastability Tolerant Computing.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

Xprova: Formal Verification Tool with Built-in Metastability Modeling.
Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017

2016
Formal verification of clock domain crossing using gate-level models of metastable flip-flops.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2014
Eliminating Synchronization Latency Using Sequenced Latching.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

An FPGA-based hardware accelerator for simulating spatiotemporal neurons.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2012
Adaptive Synchronization for DVFS Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

An RTL method for hiding clock domain crossing latency.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Intra-chip physical parameter sensor for FPGAS using flip-flop metastability.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012


  Loading...