Terrence S. T. Mak
Orcid: 0000-0003-1945-8292Affiliations:
- University of Southampton, UK
According to our database1,
Terrence S. T. Mak
authored at least 131 papers
between 2002 and 2022.
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Bibliography
2022
Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon Era.
ACM J. Emerg. Technol. Comput. Syst., 2022
2021
Molecular Type Spread Molecular Shift Keying for Multiple-Access Diffusive Molecular Communications.
IEEE Trans. Mol. Biol. Multi Scale Commun., 2021
On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip.
IEEE Trans. Computers, 2021
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach.
Integr., 2021
Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective.
IEEE Access, 2021
2020
An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Fast-Transient Response Digital Low-Dropout Regulator With Dual-Modes Tuning Technique.
IEEE Trans. Circuits Syst., 2020
A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration.
IEEE J. Solid State Circuits, 2020
On hardware-trojan-assisted power budgeting system attack targeting many core systems.
J. Syst. Archit., 2020
A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm<sup>2</sup> 7.1mW/mm<sup>2</sup> Simultaneous Wireless Inter-Tier Data and Power Transfer.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
On Runtime Communication and Thermal-Aware Application Mapping and Defragmentation in 3D NoC Systems.
IEEE Trans. Parallel Distributed Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Type-Spread Molecular Communications: Principles and Inter-Symbol Interference Mitigation.
Proceedings of the 2019 IEEE International Conference on Communications, 2019
A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects.
IEEE Trans. Emerg. Top. Comput., 2018
Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores in Many Core Systems.
IEEE Trans. Computers, 2018
A neuro-inspired visual tracking method based on programmable system-on-chip platform.
Neural Comput. Appl., 2018
Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip.
J. Syst. Archit., 2018
A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip.
J. Circuits Syst. Comput., 2018
A Genetic Algorithm with New Local Operators for Multiple Traveling Salesman Problems.
Int. J. Comput. Intell. Syst., 2018
Int. J. Geogr. Inf. Sci., 2018
Special session on bringing cores closer together: The wireless revolution in on-chip communication.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Globally Wireless Locally Wired (GloWiLoW): A Clock Distribution Network for Many-Core Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Low-power 3D integration using inductive coupling links for neurotechnology applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Parallel Distributed Syst., 2017
HRC: A 3D NoC Architecture with Genuine Support for Runtime Thermal-Aware Task Management.
IEEE Trans. Computers, 2017
CoRR, 2017
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the 2017 Forum on Specification and Design Languages, 2017
2016
Defragmentation for Efficient Runtime Resource Management in NoC-Based Many-Core Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Computers, 2016
Adaptive Routing Algorithms for Lifetime Reliability Optimization in Network-on-Chip.
IEEE Trans. Computers, 2016
Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System.
IEEE Trans. Biomed. Circuits Syst., 2016
Microprocess. Microsystems, 2016
On runtime adaptive tile defragmentation for resource management in many-core systems.
Microprocess. Microsystems, 2016
A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation.
IEEE Access, 2016
Proceedings of the 2016 International Symposium on Computer Architecture and High Performance Computing Workshops, 2016
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Sensors, 2015
An efficient runtime power allocation scheme for many-core systems inspired from auction theory.
Integr., 2015
Comput. Electr. Eng., 2015
DeFrag: Defragmentation for Efficient Runtime Resource Allocation in NoC-Based Many-core Systems.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the 10th International Conference on Future Networks and Communications (FNC 2015) / The 12th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2015) / Affiliated Workshops, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
ACM Trans. Embed. Comput. Syst., 2014
Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks.
ACM Trans. Embed. Comput. Syst., 2014
IEEE Trans. Computers, 2014
Comput. Electr. Eng., 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
A Novel Partitioning Algorithm for Optimizing Neuron-to-Neuron Pathways through NoC in BMI.
Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
Adaptive power allocation for many-core systems inspired from multiagent auction model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sources.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems.
ACM Trans. Design Autom. Electr. Syst., 2013
On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network.
IEEE Trans. Biomed. Eng., 2013
IET Comput. Digit. Tech., 2013
IET Comput. Digit. Tech., 2013
Comput. J., 2013
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
On multicast for dynamic and irregular on-chip networks using dynamic programming method.
Proceedings of the Network on Chip Architectures, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A low cost, high performance dynamic-programming-based adaptive power allocation scheme for many-core architectures in the dark silicon era.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013
Proceedings of the IEEE 11th International Conference on Dependable, 2013
Novel Multi-Layer Network Decomposition boosting acceleration of multi-core algorithms.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip.
IEEE Trans. Parallel Distributed Syst., 2012
Microelectron. J., 2012
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
A scalable FPGA-based design for field programmable large-scale ion channel simulations.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication.
Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012
2011
IEEE Trans. Ind. Electron., 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
2009
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008
2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the 3rd International IEEE Computer Society Computational Systems Bioinformatics Conference, 2004
2003
Field programmable gate arrays and analog implementation of BRIN for optimization problems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
Proceedings of the 2nd IEEE Computer Society Bioinformatics Conference, 2003
2002
Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002