Terrence S. T. Mak

According to our database1, Terrence S. T. Mak authored at least 118 papers between 2002 and 2019.

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Bibliography

2019
Design and Optimization of Inductive-Coupling Links for 3-D-ICs.
IEEE Trans. VLSI Syst., 2019

A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Type-Spread Molecular Communications: Principles and Inter-Symbol Interference Mitigation.
Proceedings of the 2019 IEEE International Conference on Communications, 2019

ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects.
IEEE Trans. Emerging Topics Comput., 2018

Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores in Many Core Systems.
IEEE Trans. Computers, 2018

A neuro-inspired visual tracking method based on programmable system-on-chip platform.
Neural Computing and Applications, 2018

Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip.
Journal of Systems Architecture - Embedded Systems Design, 2018

A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip.
Journal of Circuits, Systems, and Computers, 2018

A Genetic Algorithm with New Local Operators for Multiple Traveling Salesman Problems.
Int. J. Comput. Intell. Syst., 2018

An integrated web-based air pollution decision support system - a prototype.
International Journal of Geographical Information Science, 2018

Special session on bringing cores closer together: The wireless revolution in on-chip communication.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Globally Wireless Locally Wired (GloWiLoW): A Clock Distribution Network for Many-Core Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Improving the efficiency of thermal covert channels in multi-/many-core systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Low-power 3D integration using inductive coupling links for neurotechnology applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A high-speed design methodology for inductive coupling links in 3D-ICs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A Resilient 2-D Waveguide Communication Fabric for Hybrid Wired-Wireless NoC Design.
IEEE Trans. Parallel Distrib. Syst., 2017

HRC: A 3D NoC Architecture with Genuine Support for Runtime Thermal-Aware Task Management.
IEEE Trans. Computers, 2017

On the Nanocommunications at THz Band in Graphene-Enabled Wireless Network-on-Chip.
CoRR, 2017

On Runtime Communication- and Thermal-aware Application Mapping in 3D NoC.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Throughput Optimization for Lifetime Budgeting in Many-Core Systems.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Runtime task mapping for lifetime budgeting in many-core systems.
Proceedings of the 2017 Forum on Specification and Design Languages, 2017

2016
Defragmentation for Efficient Runtime Resource Management in NoC-Based Many-Core Systems.
IEEE Trans. VLSI Syst., 2016

IP Protection of Mesh NoCs Using Square Spiral Routing.
IEEE Trans. VLSI Syst., 2016

On Fine-Grained Runtime Power Budgeting for Networks-on-Chip Systems.
IEEE Trans. Computers, 2016

Adaptive Routing Algorithms for Lifetime Reliability Optimization in Network-on-Chip.
IEEE Trans. Computers, 2016

Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System.
IEEE Trans. Biomed. Circuits and Systems, 2016

A pareto-optimal runtime power budgeting scheme for many-core systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

On runtime adaptive tile defragmentation for resource management in many-core systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation.
IEEE Access, 2016

An Efficient Channel Model for Evaluating Wireless NoC Architectures.
Proceedings of the 2016 International Symposium on Computer Architecture and High Performance Computing Workshops, 2016

Bubble budgeting: throughput optimization for dynamic workloads by exploiting dark cores in many core systems.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

An Analytical Channel Model for Emerging Wireless Networks-on-Chip.
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

2015
Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems.
IEEE Trans. VLSI Syst., 2015

A Survey of Wireless Sensor Network Based Air Pollution Monitoring Systems.
Sensors, 2015

An efficient runtime power allocation scheme for many-core systems inspired from auction theory.
Integration, 2015

Introduction to the special issue on NoC-based many-core architectures.
Computers & Electrical Engineering, 2015

DeFrag: Defragmentation for Efficient Runtime Resource Allocation in NoC-Based Many-core Systems.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Unbiased Regional Congestion Aware Selection Function for NoCs.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

On the Design of Reliable Hybrid Wired-Wireless Network-on-Chip Architectures.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

An Improved Wireless Communication Fabric for Emerging Network-on-Chip Design.
Proceedings of the 10th International Conference on Future Networks and Communications (FNC 2015) / The 12th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2015) / Affiliated Workshops, 2015

Towards reliability and performance-aware Wireless Network-on-Chip design.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Fine-grained runtime power budgeting for networks-on-chip.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Eliminating Synchronization Latency Using Sequenced Latching.
IEEE Trans. VLSI Syst., 2014

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation.
ACM Trans. Embedded Comput. Syst., 2014

Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks.
ACM Trans. Embedded Comput. Syst., 2014

Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip.
IEEE Trans. Computers, 2014

Introduction to the Special Issue on Network-on-Chip Architectures.
Computers & Electrical Engineering, 2014

Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip.
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

A Novel Partitioning Algorithm for Optimizing Neuron-to-Neuron Pathways through NoC in BMI.
Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014

Intra- and inter-chip voltage droop analysis using a power delivery grid model.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A real-time silicon cerebellum spiking neural model based on FPGA.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A scalable FPGA-based cerebellum for passage-of-time representation.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Adaptive power allocation for many-core systems inspired from multiagent auction model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sources.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems.
ACM Trans. Design Autom. Electr. Syst., 2013

On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network.
IEEE Trans. Biomed. Engineering, 2013

Efficient multicast schemes for 3-D Networks-on-Chip.
Journal of Systems Architecture - Embedded Systems Design, 2013

Hybrid wire-surface wave interconnects for next-generation networks-on-chip.
IET Computers & Digital Techniques, 2013

Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip.
IET Computers & Digital Techniques, 2013

Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip.
Comput. J., 2013

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

On multicast for dynamic and irregular on-chip networks using dynamic programming method.
Proceedings of the Network on Chip Architectures, 2013

Towards reliable hybrid bio-silicon integration using novel adaptive control system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A low cost, high performance dynamic-programming-based adaptive power allocation scheme for many-core architectures in the dark silicon era.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

A Fault-Tolerant Routing Algorithm for NoC Using Farthest Reachable Routers.
Proceedings of the IEEE 11th International Conference on Dependable, 2013

Novel Multi-Layer Network Decomposition boosting acceleration of multi-core algorithms.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip.
IEEE Trans. Parallel Distrib. Syst., 2012

Truncation error analysis of MTBF computation for multi-latch synchronizers.
Microelectronics Journal, 2012

Surface wave communication system for on-chip and off-chip interconnects.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Intra-chip physical parameter sensor for FPGAS using flip-flop metastability.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A scalable FPGA-based design for field programmable large-scale ion channel simulations.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Minimizing power supply noise through harmonic mappings in networks-on-chip.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication.
Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

2011
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network.
IEEE Trans. Industrial Electronics, 2011

Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Communication centric on-chip power grid models for networks-on-chip.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Power adaptive computing system design in energy harvesting environment.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

On-chip dynamic programming networks using 3D-TSV integration.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Memory efficient on-line streaming for multichannel spike train analysis.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Real-time neuronal networks reconstruction using hierarchical systolic arrays.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Towards neuro-silicon interface using reconfigurable dynamic clamping.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Feasibility study for future implantable neural-silicon interface devices.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Redressing timing issues for speed-independent circuits in deep submicron age.
Proceedings of the Design, Automation and Test in Europe, 2011

Run-time deadlock detection in networks-on-chip using coupled transitive closure networks.
Proceedings of the Design, Automation and Test in Europe, 2011

Run-Time Concurrency Tuning for Peak Power Modulation in Energy Harvesting Systems.
Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011

2010
A CMOS Current-Mode Dynamic Programming Circuit.
IEEE Trans. on Circuits and Systems, 2010

Wave-pipelined intra-chip signaling for on-FPGA communications.
Integration, 2010

A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A DP-network for optimal dynamic routing in network-on-chip.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Interconnection lengths and delays estimation for communication links in FPGAs.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Global interconnections in FPGAs: modeling and performance analysis.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Implementation of Wave-Pipelined Interconnects in FPGAs.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Wave-pipelined signaling for on-FPGA communication.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

High-throughput interconnect wave-pipelining for global communication in FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

A Current-Mode Analog Circuit for Reinforcement Learning Problems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
On-FPGA Communication Architectures and Design Factors.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2004
On Computing Maximum Likelihood Phylogeny Using FPGA p.
Proceedings of the Field Programmable Logic and Application, 2004

FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation.
Proceedings of the Field Programmable Logic and Application, 2004

Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA.
Proceedings of the 3rd International IEEE Computer Society Computational Systems Bioinformatics Conference, 2004

2003
Field programmable gate arrays and analog implementation of BRIN for optimization problems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An FPGA-based eigenfilter using fast Hebbian learning.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign.
Proceedings of the 2nd IEEE Computer Society Bioinformatics Conference, 2003

2002
Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach.
Proceedings of the Field-Programmable Logic and Applications, 2002


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