Andrew D. Brown

According to our database1, Andrew D. Brown authored at least 46 papers between 1990 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 





SpiNNaker: Event-Based Simulation - Quantitative Behavior.
IEEE Trans. Multi-Scale Computing Systems, 2018

Using machine learning for sequence-level automated MRI protocol selection in neuroradiology.
JAMIA, 2018

The European Masters in Embedded Computing Systems (EMECS).
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

SpiNNaker - Programming Model.
IEEE Trans. Computers, 2015

Reliable computation with unreliable computers.
IET Computers & Digital Techniques, 2015

A Tracking System for Wireless Embedded Nodes Using Time-of-Flight Ranging.
IEEE Trans. Mob. Comput., 2013

Overview of the SpiNNaker System Architecture.
IEEE Trans. Computers, 2013

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation.
J. Solid-State Circuits, 2013

Interconnection system for the spiNNaker biologically inspired multi-computer.
IET Computers & Digital Techniques, 2013

Atomic computing - a different perspective on massively parallel problems.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

Behavioural synthesis utilising recursive definitions.
IET Computers & Digital Techniques, 2012

Processing with a million cores.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

A communication infrastructure for a million processor machine.
Proceedings of the 7th Conference on Computing Frontiers, 2010

The biometric potential of transient otoacoustic emissions.
IJBM, 2009

Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors.
Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009

SpiNNaker: The Design Automation Problem.
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008

Yield model characterization for analog integrated circuit using Pareto-optimal surface.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

Behavioural Simulation and Synthesis of Biological Neuron Systems using VHDL.
Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008

Power aware learning for class AB analogue VLSI neural network.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On-chip and inter-chip networks for modeling large-scale neural systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Power scalable implementation of Artificial Neural Networks.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

A behavioral synthesis system for asynchronous circuits.
IEEE Trans. VLSI Syst., 2004

Behavioural modelling of analogue faults in VHDL-AMS - a case study.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Multiple domain behavioral modeling using VHDL-AMS.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Using Otoacoustic Emissions as a Biometric.
Proceedings of the Biometric Authentication, First International Conference, 2004

Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS.
Proceedings of the 2004 Design, 2004

A General Purpose Behavioural Asynchronous Synthesis System.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

The continuous-discrete interface - What does this really mean? Modelling and simulation issues.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A large-scale simulation of the piriform cortex by a cell automaton-based network model.
IEEE Trans. Biomed. Engineering, 2002

Discrete simulation of large aggregates of neurons.
Neurocomputing, 2002

Scalable cortical simulations on Beowulf architectures.
Neurocomputing, 2002

Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS.
Proceedings of the 2002 Design, 2002

Floating-point behavioral synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Relative Density Nets: A New Way to Combine Backpropagation with HMM's.
Proceedings of the Advances in Neural Information Processing Systems 14 [Neural Information Processing Systems: Natural and Synthetic, 2001

Products of Hidden Markov Models.
Proceedings of the Eighth International Workshop on Artificial Intelligence and Statistics, 2001

A parallel-connected active filter for the reduction of supply current distortion.
IEEE Trans. Industrial Electronics, 2000

BIST hardware synthesis for RTL data paths based on testcompatibility classes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Cooperative Coevolution of Neural Representations.
Int. J. Neural Syst., 2000

A contactless electrical energy transmission system.
IEEE Trans. Industrial Electronics, 1999

Cooperative-Competitive Algorithms for Evolutionary Networks Classifying Noisy Digital Images.
Neural Processing Letters, 1999

Spiking Boltzmann Machines.
Proceedings of the Advances in Neural Information Processing Systems 12, [NIPS Conference, Denver, Colorado, USA, November 29, 1999

On-line testing of statically and dynamically scheduled synthesized systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Confidence in mixed-mode circuit simulation.
Computer-Aided Design, 1992

A General Purpose Network Solving System.
VLSI, 1991

Lee router modified for global routing.
Computer-Aided Design, 1990