Giovanni Cesura

According to our database1, Giovanni Cesura authored at least 7 papers between 1993 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET.
IEEE J. Solid State Circuits, 2020

2019

2013
A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS.
IEEE J. Solid State Circuits, 2013

2012
A 40MHz-to-1GHz fully integrated multistandard silicon tuner in 80nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2009
A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006
A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

1993
A BiCMOS Tunable Shaper for Detectors of Elementary Particles.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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