Gordon R. Chiu

According to our database, Gordon R. Chiu authored at least 9 papers between 2006 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Flexibility: FPGAs and CAD in Deep Learning Acceleration.

Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah

Proceedings of the 2018 International Symposium on Physical Design, 2018

Harnessing Numerical Flexibility for Deep Learning on FPGAs.

Andrew C. Ling, Mohamed S. Abdelfattah, Shane O'Connell, Andrew Bitar, David Han, Roberto DiCecco, Suchit Subhaschandra, Chris N. Johnson, Dmitry Denisenko, Joshua Fender, Gordon R. Chiu

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration.

Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.

Andrew C. Ling, Utku Aydonat, Shane O'Connell, Davor Capalija, Gordon R. Chiu

Proceedings of the 5th International Workshop on OpenCL, 2017

An OpenCL™ Deep Learning Accelerator on Arria 10.

Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

The Stratix™ 10 Highly Pipelined FPGA Architecture.

David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2007

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown

IEEE Trans. Very Large Scale Integr. Syst., 2007

2006

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs.

Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006