Deshanand P. Singh

According to our database, Deshanand P. Singh authored at least 32 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision.

Ahmed F. AbouElhamayed, Susanne Balle, Deshanand P. Singh, Mohamed S. Abdelfattah

CoRR, 2024

Primate: A Framework to Automatically Generate Soft Processors for Network Applications.

Rui Ma, Jia-Ching Hsu, Ali Mansoorshahi, Joseph Garvey, Michael Kinsner, Deshanand P. Singh, Derek Chiou

IEEE Comput. Archit. Lett., 2024

2023

A Software-Hardware Co-Optimized Toolkit for Deep Reinforcement Learning on Heterogeneous Platforms.

Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A Iyer, Viktor K. Prasanna

CoRR, 2023

2016

OpenCL.

Deshanand P. Singh, Peter Yiannacouras

Proceedings of the FPGAs for Software Programmers, 2016

2015

High-Level Design Tools for Floating Point FPGAs.

Deshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014

Gzip on a chip: high performance lossless data compression on FPGAs using OpenCL.

Mohamed S. Abdelfattah, Andrei Hagiescu, Deshanand P. Singh

Proceedings of the International Workshop on OpenCL, 2014

2013

Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applications.

Doris Chen, Deshanand P. Singh

ACM Trans. Archit. Code Optim., 2013

Harnessing the power of FPGAs using altera's OpenCL compiler.

Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms.

Doris Chen, Deshanand P. Singh

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

From opencl to high-performance hardware on FPGAS.

Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering.

Doris Chen, Deshanand P. Singh

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

Line-level incremental resynthesis techniques for FPGAs.

Doris Chen, Deshanand P. Singh

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs).

Doris Chen, Deshanand P. Singh

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.

Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2007

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown

IEEE Trans. Very Large Scale Integr. Syst., 2007

FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability.

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An area-efficient timing closure technique for FPGAs using Shannon's expansion.

Deshanand P. Singh, Stephen Dean Brown

Integr., 2007

Incremental placement for structured ASICs using the transportation problem.

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the IFIP VLSI-SoC 2007, 2007

2006

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs.

Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

FPGA Logic Synthesis Using Quantified Boolean Satisfiability.

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the Theory and Applications of Satisfiability Testing, 2005

Post-Placement BDD-Based Decomposition for FPGAs.

Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

FPGA PLB Evaluation using Quantified Boolean Satisfiability.

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Incremental retiming for FPGA physical synthesis.

Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown

Proceedings of the 42nd Design Automation Conference, 2005

FPGA technology mapping: a study of optimality.

Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 42nd Design Automation Conference, 2005

Two-stage physical synthesis for FPGAs.

Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

The Quartus University Interface Program: enabling advanced FPGA research.

Shawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

2003

Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices.

Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown

Proceedings of the International Conference on VLSI, 2003

2002

Incremental placement for layout driven optimizations on FPGAs.

Deshanand P. Singh, Stephen Dean Brown

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Constrained clock shifting for field programmable gate arrays.

Deshanand P. Singh, Stephen Dean Brown

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Integrated retiming and placement for field programmable gate arrays.

Deshanand P. Singh, Stephen Dean Brown

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001

The case for registered routing switches in field programmable gate arrays.

Deshanand P. Singh, Stephen Dean Brown

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001