Graham Hetherington

According to our database1, Graham Hetherington authored at least 7 papers between 1990 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
A Holistic Parallel and Hierarchical Approach towards Design-For-Test.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Circular BIST testing the digital logic within a high speed Serdes.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

1999
Logic BIST for large industrial designs: real issues and case studies.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1995
Test Generation and Design for Test for a Large Multiprocessing DSP.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1990
High-Level Synthesis: Technology Transfer to Industry.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990


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