Gordon J. Brebner

According to our database1, Gordon J. Brebner authored at least 51 papers between 1981 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2019
Optimizing Validation Phase of Hyperledger Fabric.
Proceedings of the 27th IEEE International Symposium on Modeling, 2019

Event-Driven Packet Processing.
Proceedings of the 18th ACM Workshop on Hot Topics in Networks, 2019

The P4->NetFPGA Workflow for Line-Rate Packet Processing.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

FastProxy: Hardware and Software Acceleration of Stratum Mining Proxy.
Proceedings of the Crypto Valley Conference on Blockchain Technology, 2019

2017
Whippersnapper: A P4 Language Benchmark Suite.
Proceedings of the Symposium on SDN Research, 2017

2014
High-Speed Packet Processing using Reconfigurable Computing.
IEEE Micro, 2014

2013
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems.
TRETS, 2013

2012
Optimizing packet lookup in time and space on FPGA.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Softly defined networking.
Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012

2011
Reconfigurable Computing for High Performance Networking Applications.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

400 Gb/s Programmable Packet Parsing on a Single FPGA.
Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

2010
Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009
Packets everywhere: The great opportunity for field programmable technology.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

2008
OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems.
SIGARCH Computer Architecture News, 2008

2007
Editorial for the Special Issue on Field Programmable Technology.
VLSI Signal Processing, 2007

2006
Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Building a flexible and scalable DRAM interface for networking applications on FPGAs.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Systematic Characterization of Programmable Packet Processing Pipelines.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Memory centric thread synchronization on platform FPGAs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

06141 Abstracts Collection -- Dynamically Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

06141 Executive Summary -- Dynamically Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

2005
Mutable Codesign for Embedded Protocol Processing.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Programming a hyper-programmable architecture for networked systems.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Multithreading in a Hyper-programmable Platform for Networked Systems.
Proceedings of the Field Programmable Logic and Application, 2004

Programmable Logic Has More Computational Power than Fixed Logic.
Proceedings of the Field Programmable Logic and Application, 2004

Time-Critical Software Deceleration in an FCCM.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Mapping a domain specific language to a platform FPGA.
Proceedings of the 41th Design Automation Conference, 2004

Hyper-Programmable Architectures for Adaptable Networked Systems.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Networking on chip with platform FPGAs.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Software Decelerators.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Eccentric SoC Architectures as the Future Norm.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002
Workshop Introduction.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Multithreading for Logic-Centric Systems.
Proceedings of the Field-Programmable Logic and Applications, 2002

Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
Chip-Based Reconfigurable Task Management.
Proceedings of the Field-Programmable Logic and Applications, 2001

Circlets: Circuitry over the Internet.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

1999
A Transactional Approach to Configuring Telecommunications Services.
Proceedings of the Databases in Telecommunications, 1999

Reconfigurable Computing in Remote and Harsh Environments.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1998
Runtime Reconfigurable Routing.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

An Interactive Datasheet for the Xilinx XC6200.
Proceedings of the Field-Programmable Logic and Applications, 1998

Field-Programmable Logic: Catalyst for New Computing Paradigms.
Proceedings of the Field-Programmable Logic and Applications, 1998

Circlets: Circuits as Applets.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

ECOLE: A Configurable Environment for a Local Optical Network of Workstations.
Proceedings of the Network-Based Parallel Computing: Communication, 1998

1997
Automatc identification of swappable logic units in XC6200 circuitry.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

The swappable logic unit: a paradigm for virtual hardware.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1996
A Virtual Hardware Operating System for the Xilinx XC6200.
Proceedings of the Field-Programmable Logic, 1996

1995
Use of Reconfigurability in Variable-Length Code Detection at Video Rates.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

1993
Configurable array logic circuits for computing network error detection codes.
VLSI Signal Processing, 1993

A CCS-based Investigation of Deadlock in a Multi-process Electronic Mail System.
Formal Asp. Comput., 1993

1981
Universal Schemes for Parallel Communication
Proceedings of the 13th Annual ACM Symposium on Theory of Computing, 1981


  Loading...