Hachiro Yamada

According to our database, Hachiro Yamada authored at least 6 papers between 1994 and 1997.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1997

Floating-point datapaths with online built-in self speed test.

Yasuhiko Hagihara, Shigeto Inui, Fuyuki Okamoto, Masato Nishida, Toshihiko Nakamura, Hachiro Yamada

IEEE J. Solid State Circuits, 1997

1996

A GHz MOS adaptive pipeline technique using MOS current-mode logic.

Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada

IEEE J. Solid State Circuits, 1996

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies.

Tohru Miwa, Hachiro Yamada, Yoshinori Hirota, Toshiya Satoh, Hideki Hara

IEEE J. Solid State Circuits, 1996

1995

Cache-processor coupling: a fast and wide on-chip data cache design.

Masato Motomura, Toshiaki Inoue, Hachiro Yamada, Akihiko Konagaya

IEEE J. Solid State Circuits, April, 1995

1994

A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor.

Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada

IEEE J. Solid State Circuits, December, 1994

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI.

Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada

IEEE J. Solid State Circuits, March, 1994