Tadayoshi Enomoto

According to our database1, Tadayoshi Enomoto authored at least 28 papers between 1984 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1998, "For contributions to the development of integrated circuits multimedia.".

Timeline

Legend:

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In proceedings 
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Links

On csauthors.net:

Bibliography

2023
Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption.
IEICE Trans. Electron., September, 2023

2019
Low standby power CMOS delay flip-flop with data retention capability.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Development of a high stability, low standby power six-transistor CMOS SRAM employing a single power supply.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Development of a Low Standby Power Six-Transistor CMOS SRAM Employing a Single Power Supply.
IEICE Trans. Electron., 2018

Quantized Decoder Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for a Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor.
IEICE Trans. Electron., 2018

2015
A high stability, low supply voltage and low standby power six-transistor CMOS SRAM.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2013
A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called "Adaptively Assigned Breaking-Off Condition (A<sup>2</sup>BC)".
IEICE Trans. Electron., 2013

A low power multimedia processor implementing dynamic voltage and frequency scaling technique.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2011
A Large "Read" and "Write" Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM.
IEICE Trans. Electron., 2011

2009
Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit.
IEICE Trans. Electron., 2009

Foreword.
IEICE Trans. Electron., 2009

Fast Sub-sampling Block Matching Algorithm Employing Adaptively Assigned Sizes and Locations of Search Windows.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array.
IEICE Trans. Electron., 2008

A low power 90-nm CMOS motion estimation processor implementing dynamic voltage and frequency scaling (DVFS) and fast motion estimation algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A low-leakage current power 180-nm CMOS SRAM.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
A Multiple Block-matching Step (MBS) Algorithm for H.26x/MPEG4 Motion Estimation and a Low-Power CMOS Absolute Differential Accumulator Circuit.
IEICE Trans. Electron., 2007

Low-Power High-Speed 180-nm CMOS Clock Drivers.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits.
IEICE Trans. Electron., 2006

A low dynamic power and low leakage power 90-nm CMOS square-root circuit.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
A low dynamic power and low leakage power CMOS square-root circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications.
IEEE J. Solid State Circuits, 2003

2001
A fast motion estimation algorithm and low-power 0.13-um CMOS motion estimation circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999
Fast motion estimation algorithm and low-power CMOS motion estimation array LSI for MPEG-2 encoding.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1994
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI.
IEEE J. Solid State Circuits, March, 1994

1988
A single-board video signal processor module employing newly developed LSI devices.
IEEE J. Sel. Areas Commun., 1988

1987
Realtime video signal processor module.
Proceedings of the IEEE International Conference on Acoustics, 1987

1986
Video signal processor configuration by multiprocessor approach.
Proceedings of the IEEE International Conference on Acoustics, 1986

1984
Single-Chip Adaptive Transversal Filter IC Employing Switched Capacitor Technology.
IEEE J. Sel. Areas Commun., 1984


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